Hironori Nakajo

Pulung Waskito, Shinobu Miwa, Yasue Mitsukura, Hironori Nakajo: Evaluation of GPU-Based Empirical Mode Decomposition for Off-Line Analysis. IEICE Transactions 94-D(12): 2328-2337 (2011)

Trang Thuy Vu, Akifumi Sokan, Hironori Nakajo, Kaori Fujinami, Jaakko Suutala, Pekka Siirtola, Tuomo Alasalmi, Ari Pitkänen, Juha Röning: Detecting water waste activities for water-efficient living. Ubicomp 2011: 579-580

Hironori Nakajo, Keisuke Koike, Atsushi Ohta, Kohta Ohshima, Kaori Fujinami: Reconfigurable Android with an FPGA Accelerator for the Future Embedded Devices. ICNC 2011: 173-178

Trang Thuy Vu, Akifumi Sokan, Hironori Nakajo, Kaori Fujinami, Jaakko Suutala, Pekka Siirtola, Tuomo Alasalmi, Ari Pitkänen, Juha Röning: Feature Selection and Activity Recognition to Detect Water Waste from Water Tap Usage. RTCSA (2) 2011: 138-141

Noboru Tanabe, Hirotaka Hakozaki, Hiroshi Ando, Yasunori Dohi, Zhengzhe Luo, Hironori Nakajo: An enhancer of memory and network for applications with large-capacity data and non-continuous data accessing. The Journal of Supercomputing 51(3): 279-309 (2010)

Hiroki Yokoyama, Yuhei Horibe, Peng Zhang, Shinobu Miwa, Hironori Nakajo: An Effective Replacement Policy Focusing on Lifetime of a Cache Line. CDES 2010: 146-152

Pulung Waskito, Shinobu Miwa, Yasue Mitsukura, Hironori Nakajo: Parallelizing Hilbert-Huang Transform on a GPU. ICNC 2010: 184-190

Noboru Tanabe, Hironori Nakajo: Acceleration for MPI derived datatypes using an enhancer of memory and network. IPDPS Workshops 2010: 1-6

Yoshiyasu Ogasawara, Pulung Waskito, Shinobu Miwa, Hironori Nakajo: Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor. CDES 2009: 171-177

Yoshiyasu Ogasawara, Hironori Nakajo: An Effective Replacement Strategy of Cache Memory for an SMT Processor. DSD 2009: 19-25

Noboru Tanabe, Atsushi Ohta, Pulung Waskito, Hironori Nakajo: Network Interface Architecture for Scalable Message Queue Processing. ICPADS 2009: 268-275

Noboru Tanabe, Manami Sasaki, Hironori Nakajo, Masami Takata, Kazuki Joe: The architecture of visualization system using memory with memory-side gathering and CPUs with DMA-type memory accessing. PDPTA 2009: 427-433

Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, Shinji Tomita: Low-Complexity Bypass Network Using Small RAM. CDES 2008: 153-159

Noboru Tanabe, Hironori Nakajo: An Enhancer of Memory and Network for Cluster and its Applications. PDCAT 2008: 99-106

Noboru Tanabe, Hironori Nakajo: Introduction to Acceleration for MPI Derived Datatypes Using an Enhancer of Memory and Network. PVM/MPI 2008: 324-325

Kenji Kise, Toshinori Sato, Hironori Nakajo: Introduction. SIGARCH Computer Architecture News 35(5): 1-2 (2007)

Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano: Performance evaluation on low-latency communication mechanism of DIMMnet-2. Parallel and Distributed Computing and Networks 2007: 57-62

Atsushi Ohta, Yoshihiro Hamada, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo: Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot. PDPTA 2007: 787-793

Satoshi Watanabe, Yoshiyasu Ogasawara, Ippei Tate, Hirofumi Yano, Hironori Nakajo: Toward Parallel and Distributed Processing on High-Density Network with Mobile Devices. PDPTA 2007: 794-800

Tomotaka Miyashiro, Akira Kitamura, Hironori Nakajo, Noboru Tanabe: DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot. FPL 2006: 1-4

Jun Kanai, Takuro Mori, Takeshi Araki, Noboru Tanabe, Hironori Nakajo, Mitaro Namiki: Implementation of PC Cluster System with Memory Mapped File by Commodity OS. PDPTA 2006: 902-908

Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo: A Model of Implementable SMT Processor on FPGA. PDPTA 2006: 909-915

Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo: Towards Reconfigurable Cache Memory for a Multithreaded Processor. PDPTA 2006: 916-924

Yasuo Miyabe, Akira Kitamura, Yoshihiro Hamada, Tomotaka Miyashiro, Tetsu Izawa, Noboru Tanabe, Hironori Nakajo, Hideharu Amano: Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2. ISHPC 2005: 211-218

Akira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo: Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board. PDCAT 2005: 778-780

Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo: A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. PDPTA 2005: 447-453

Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki: Development of a Thread Scheduler for SMT Processor Architecture. PDPTA 2005: 454-460

Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo: A Packet Forwarding Layer for DIMMnet and its Hardware Implementation. PDPTA 2005: 461-467

Noboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano: A New Memory Module for Memory Intensive Applications. PARELEC 2004: 123-128

Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo: Dynamic Allocation of Physical Register Banks for an SMT Processor. PDPTA 2004: 317-323

Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki: Implementation and Evaluation of a Thread Library for Multithreaded Architecture. PDPTA 2003: 609-615

Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki: A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. PDPTA 2003: 1669-1675

Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki: Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. PDPTA 2003: 1775-1781

Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano: Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot. Cluster Computing 5(1): 7-17 (2002)

Noboru Tanabe, Yoshihiro Hamada, Hironori Nakajo, Hideki Imashiro, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano: Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot. PARELEC 2002: 9-14

Hironori Nakajo, Akihiro Ichikawa, Yukio Kaneda: A Distributed Shared-Memory System on a Workstation Cluster Using Fast Serial Links. International Journal of Parallel Programming 28(2): 179-194 (2000)

Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano: MEMOnet : Network interface plugged into a memory slot. CLUSTER 2000: 17-16

Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano: On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism. ISPAN 2000: 186-194

Hironori Nakajo, M. Ishii, T. Kudo, Hideharu Amano: Coherence Protocol for Home Proxy Cache on RHiNET. PDPTA 2000

Hironori Nakajo, Hidekazu Tanaka, Yoshinori Nakanishi, Masaki Kohata, Yukio Kaneda: Distributed Shared-Memory for a Workstation Cluster with a High Speed Serial Interface. HPCN Europe 1998: 588-597

Hironori Nakajo, Satoshi Ohtani, Takashi Matsumoto, Masadi Kohata, Kei Hiraki, Yukio Kaneda: An I/O Network Architecture of the Distributed Shared-Memory Massively Parallel Computer JUMP-1. International Conference on Supercomputing 1997: 253-260

Hironori Nakajo, Akihiro Ichikawa, Yukio Kaneda: An Implementation and Evaluation of a Distributed Shared-Memory System on Workstation Clusters Using Fast Serial Links. ISHPC 1997: 143-158

Hironori Nakajo, Satoshi Ohtani, Yukio Kaneda: A Simulation-based Evaluation of a Disk I/O Subsystem for a Massively Parallel Computer: JUMP-1. ICDCS 1996: 562-569

Hironori Nakajo, Takashi Matsumoto, Masaki Kohata, Hideo Matsuda, Kei Hiraki, Yukio Kaneda: High Performance I/O System of the Distributed Shared-Memory Massively Parallel Computer JUMP-1. Parallel and Distributed Computing and Systems 1995: 470-473