Andreas Moshovos

Michel El-Nacouzi, Islam Atta, Myrto Papadopoulou, Jason Zebchuk, Natalie D. Enright Jerger, Andreas Moshovos: A dual grain hit-miss detector for large die-stacked DRAM caches. DATE 2013: 89-92

Vitaly Zakharenko, Tor M. Aamodt, Andreas Moshovos: Characterizing the performance benefits of fused CPU/GPU systems using FusionSim. DATE 2013: 685-688

Kaveh Aasaraai, Andreas Moshovos: NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution. Int. J. Reconfig. Comp. 2012 (2012)

Ioana Burcea, Livio Soares, Andreas Moshovos: Pointy: a hybrid pointer prefetcher for managed runtime systems. PACT 2012: 97-106

Jason Zebchuk, Harold W. Cain, Vijayalakshmi Srinivasan, Andreas Moshovos: ReCaP: a region-based cure for the common cold cache. PACT 2012: 443-444

Islam Atta, Pinar Tözün, Anastasia Ailamaki, Andreas Moshovos: Reducing OLTP instruction misses with thread migration. DaMoN 2012: 9-15

Maryam Sadooghi-Alvandi, Kaveh Aasaraai, Andreas Moshovos: Toward virtualizing branch direction prediction. DATE 2012: 455-460

Islam Atta, Pinar Tözün, Anastasia Ailamaki, Andreas Moshovos: SLICC: Self-Assembly of Instruction Cache Collectives for OLTP Workloads. MICRO 2012: 188-198

Kaveh Aasaraai, Andreas Moshovos: SPREX: A soft processor with Runahead execution. ReConFig 2012: 1-7

Elham Safi, Andreas Moshovos, Andreas G. Veneris: Two-Stage, Pipelined Register Renaming. IEEE Trans. VLSI Syst. 19(10): 1926-1931 (2011)

Carlo Galuzzi, Luigi Carro, Andreas Moshovos, Milos Prvulovic (Eds.): 44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, 3-7 December 2011, Porto Alegre, Brazil. ACM 2011, isbn 978-1-4503-1053-6

Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos: Making Address-Correlated Prefetching Practical. IEEE Micro 30(1): 50-59 (2010)

Elham Safi, Andreas Moshovos, Andreas G. Veneris: On the Latency and Energy of Checkpointed Superscalar Register Alias Tables. IEEE Trans. VLSI Syst. 18(3): 365-377 (2010)

Kaveh Aasaraai, Andreas Moshovos: Design space exploration of instruction schedulers for out-of-order soft processors. FPT 2010: 385-388

Henry Wong, Misel-Myrto Papadopoulou, Maryam Sadooghi-Alvandi, Andreas Moshovos: Demystifying GPU microarchitecture through microbenchmarking. ISPASS 2010: 235-246

Kaveh Aasaraai, Andreas Moshovos: An Efficient Non-blocking Data Cache for Soft Processors. ReConFig 2010: 19-24

Andreas Moshovos, J. Gregory Steffan, Kim M. Hazelwood, David R. Kaeli (Eds.): Proceedings of the CGO 2010, The 8th International Symposium on Code Generation and Optimization, Toronto, Ontario, Canada, April 24-28, 2010. ACM 2010, isbn 978-1-60558-635-9

Ioana Burcea, Andreas Moshovos: Phantom-BTB: a virtualized branch target buffer design. ASPLOS 2009: 313-324

Kaveh Aasaraai, Andreas Moshovos: Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming. FPL 2009: 79-85

Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos: Practical off-chip meta-data for temporal memory streaming. HPCA 2009: 79-90

Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin K. Qureshi, Andreas Moshovos: A tagless coherence directory. MICRO 2009: 423-434

Elham Safi, Andreas Moshovos, Andreas G. Veneris: A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors. ICSAMOS 2009: 41-48

Elham Safi, Andreas Moshovos, Andreas G. Veneris: L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture. IEEE Trans. VLSI Syst. 16(6): 628-638 (2008)

Ioana Burcea, Stephen Somogyi, Andreas Moshovos, Babak Falsafi: Predictor virtualization. ASPLOS 2008: 157-167

Patrick Akl, Andreas Moshovos: Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator. HiPEAC 2008: 258-272

Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos: Temporal streams in commercial server applications. IISWC 2008: 99-108

Elham Safi, Andreas Moshovos, Andreas G. Veneris: A physical level study and optimization of CAM-based checkpointed register alias table. ISLPED 2008: 233-236

Michael Ferdman, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos: Temporal instruction fetch streaming. MICRO 2008: 1-10

Andreas Moshovos, David Tarditi, Kunle Olukotun (Eds.): 17th International Conference on Parallel Architecture and Compilation Techniques (PACT 2008), Toronto, Ontario, Canada, October 25-29, 2008. ACM 2008, isbn 978-1-60558-282-5

Jason Zebchuk, Andreas Moshovos: A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy. Computer Architecture Letters 6(2): 33-36 (2007)

Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos: Mechanisms for store-wait-free multiprocessors. ISCA 2007: 266-277

Elham Safi, Patrick Akl, Andreas Moshovos, Andreas G. Veneris, Aggeliki Arapoyanni: On the latency, energy and area of checkpointed, superscalar register alias tables. ISLPED 2007: 379-382

Jason Zebchuk, Elham Safi, Andreas Moshovos: A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy. MICRO 2007: 314-327

Jason F. Cantin, James E. Smith, Mikko H. Lipasti, Andreas Moshovos, Babak Falsafi: Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays. IEEE Micro 26(1): 70-79 (2006)

Patrick Akl, Andreas Moshovos: BranchTap: improving performance with very few checkpoints through adaptive speculation control. ICS 2006: 36-45

Stephen Somogyi, Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos: Spatial Memory Streaming. ISCA 2006: 252-263

Elham Safi, Andreas Moshovos, Andreas G. Veneris: L-CBF: a low-power, fast counting bloom filter architecture. ISLPED 2006: 250-255

Andreas Moshovos, Babak Falsafi, Farid N. Najm, Navid Azizi: A Case for Asymmetric-Cell Cache Memories. IEEE Trans. VLSI Syst. 13(7): 877-881 (2005)

Andreas Moshovos, Alexandros Kostopoulos: Memory State Compressors for Giga-Scale Checkpoint/Restore. IEEE PACT 2005: 303-314

Won-Ho Park, Andreas Moshovos, Babak Falsafi: RECAST: Boosting Tag Line Buffer Coverage in Low-Power High-Level Caches "for Free". ICCD 2005: 609-616

Andreas Moshovos: RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence. ISCA 2005: 234-245

Chi F. Chen, Se-Hyun Yang, Babak Falsafi, Andreas Moshovos: Accurate and Complexity-Effective Spatial Pattern Prediction. HPCA 2004: 276-287

Amirali Baniasadi, Andreas Moshovos: SEPAS: a highly accurate energy-efficient branch predictor. ISLPED 2004: 38-43

Ahmed Abdelkhalek, Angelos Bilas, Andreas Moshovos: Behavior and Performance of Interactive Multi-Player Game Servers. Cluster Computing 6(4): 355-366 (2003)

Navid Azizi, Farid N. Najm, Andreas Moshovos: Low-leakage asymmetric-cell SRAM. IEEE Trans. VLSI Syst. 11(4): 701-715 (2003)

Andreas Moshovos: Checkpointing alternatives for high performance, power-aware processors. ISLPED 2003: 318-321

Andreas Moshovos, Gurindar S. Sohi: Reducing Memory Latency via Read-after-Read Memory Dependence Prediction. IEEE Trans. Computers 51(3): 313-326 (2002)

Amirali Baniasadi, Andreas Moshovos: Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors. ICCD 2002: 458-461

Navid Azizi, Andreas Moshovos, Farid N. Najm: Low-leakage asymmetric-cell SRAM. ISLPED 2002: 48-51

Amirali Baniasadi, Andreas Moshovos: Asymmetric-frequency clustering: a power-aware back-end for high-performance processors. ISLPED 2002: 255-258

Andreas Moshovos, Gokhan Memik, Babak Falsafi, Alok N. Choudhary: JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers. HPCA 2001: 85-96

Andreas Moshovos, Dionisios N. Pnevmatikatos, Amirali Baniasadi: Slice-processors: an implementation of operation-based prediction. ICS 2001: 321-334

Amirali Baniasadi, Andreas Moshovos: Instruction flow-based front-end throttling for power-aware high-performance processors. ISLPED 2001: 16-21

Andreas Moshovos, Gurindar S. Sohi: Memory Dependence Prediction in Multimedia Applications. J. Instruction-Level Parallelism 2 (2000)

Andreas Moshovos, Gurindar S. Sohi: Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors. HPCA 2000: 301-312

Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithviraj Banerjee: CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit. ISCA 2000: 225-235

Amirali Baniasadi, Andreas Moshovos: Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors. MICRO 2000: 337-347

Andreas Moshovos, Gurindar S. Sohi: Speculative Memory Cloaking and Bypassing. International Journal of Parallel Programming 27(6): 427-456 (1999)

Amir Roth, Andreas Moshovos, Gurindar S. Sohi: Improving virtual function call target prediction via dependence-based pre-computation. International Conference on Supercomputing 1999: 356-364

Andreas Moshovos, Gurindar S. Sohi: Read-After-Read Memory Dependence Prediction. MICRO 1999: 177-185

Amir Roth, Andreas Moshovos, Gurindar S. Sohi: Dependance Based Prefetching for Linked Data Structures. ASPLOS 1998: 115-126

Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi: Dynamic Speculation and Synchronization of Data Dependences. ISCA 1997: 181-193

Andreas Moshovos, Gurindar S. Sohi: Streamlining Inter-Operation Memory Communication via Data Dependence Prediction. MICRO 1997: 235-245