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 | 2012 | |
|---|---|---|
| j9 |      | Tomoaki Ando, Vasily G. Moshnyaga, Koji Hashimoto: FPGA Design of User Monitoring System for Display Power Control. IEICE Transactions 95-A(12): 2364-2372 (2012) |
| j8 | | Vasily G. Moshnyaga, Koji Hashimoto, Tadashi Suetsugu: A Camera-Driven Power Management of Computer Display. IEEE Trans. Circuits Syst. Video Techn. 22(11): 1542-1553 (2012) |
| c46 | | Tomoaki Ando, Vasily G. Moshnyaga, Koji Hashimoto: A low-power FPGA implementation of eye tracking. ICASSP 2012: 1573-1576 |
| 2011 | ||
| c45 | | Choong Geun Lee, Vasily G. Moshnyaga, Koji Hashimoto: Embedded System for Camera-Based TV Power Reduction. DSD 2011: 764-768 |
| c44 | | Chungun Lee, Vasily G. Moshnyaga: Embedded system for TV power reduction by viewer monitoring. ICME 2011: 1-4 |
| c43 | | Choong Geun Lee, Vasily G. Moshnyaga: TV energy management by camera-based viewer monitoring. ISCAS 2011: 949-952 |
| 2010 | ||
| c42 |  | Koji Hashimoto, Vasily G. Moshnyaga: A Cost-Effective TCP/IP Offload Accelerator Design for Network Interface Controller. CDES 2010: 153-159 |
| c41 | | |
| c40 | | Vasily G. Moshnyaga: A new approach for energy management in user-centric applications. Green Computing Conference 2010: 107-112 |
| c39 | | Takeaki Matsubara, Vasily G. Moshnyaga, Koji Hashimoto: A FPGA implementation of low-complexity noise removal. ICECS 2010: 255-258 |
| 2009 | ||
| c38 | | Vasily G. Moshnyaga, Koji Hashimoto, Shuhei Higashi: A Hardware System for Tracking Eyes of Computer User. CDES 2009: 125-130 |
| c37 | | Vasily G. Moshnyaga, Koji Hashimoto, Tadashi Suetsugu, Shuhei Higashi: A Hardware Implementation of the User-Centric Display Energy Management. PATMOS 2009: 56-65 |
| c36 | | Vasily G. Moshnyaga, Shinji Yamamoto: Algorithm Optimizations for Low-Complexity Eye Tracking. SMC 2009: 18-22 |
| 2008 | ||
| c35 | | |
| c34 | | Vasily G. Moshnyaga, Koji Hashimoto, Tadashi Suetsugu: A Hardware Design for Camera-Based Power Management of Computer Monitor. DSD 2008: 203-209 |
| c33 | | |
| c32 | | Vasily G. Moshnyaga, Koji Hashimoto, Tadashi Suetsugu: A hardware design of camera-based user's presence detector. SMC 2008: 429-432 |
| 2007 | ||
| c31 | | Vasily G. Moshnyaga, Hua Vo, Glenn Reinman, Miodrag Potkonjak: Reducing Energy of DRAM/Flash Memory System by OS-controlled Data Refresh. ISCAS 2007: 2108-2111 |
| 2006 | ||
| c30 | | Koji Hashimoto, Vasily G. Moshnyaga, Kazuaki Murakami: Circuit Area-latency Optimization Technique for High-precision Elementary Functions. APCCAS 2006: 1406-1409 |
| c29 | | |
| c28 | | Vasily G. Moshnyaga, S. Yamaoka: MPEG complexity reduction by scene adaptive motion estimation. ISCAS 2006 |
| c27 | | Vasily G. Moshnyaga, Hoa Vo, Glenn Reinman, Miodrag Potkonjak: Handheld System Energy Reduction by OS-Driven Refresh. PATMOS 2006: 24-35 |
| 2005 | ||
| j7 | | Reiko Komiya, Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches. IEICE Transactions 88-A(4): 862-868 (2005) |
| j6 | | Vasily G. Moshnyaga, Tomoyuki Yamanaka: Multiplier Energy Reduction by Dynamic Voltage Variation. IEICE Transactions 88-A(12): 3548-3553 (2005) |
| c26 | | Vasily G. Moshnyaga, Naoki Migita, Kenji Wakisaka: Reduction of MPEG2 video decoding computations. Circuits, Signals, and Systems 2005: 218-221 |
| c25 | | Vasily G. Moshnyaga, Eiji Morikawa: LCD Display Energy Reduction by User Monitoring. ICCD 2005: 94-97 |
| c24 | | Vasily G. Moshnyaga, Eiji Morikawa: Reducing Energy Consumption of Computer Display by Camera-Based User Monitoring. PATMOS 2005: 528-539 |
| 2004 | ||
| c23 | | Kentaro Hamayasu, Vasily G. Moshnyaga: Impact of Register-Cache Bandwidth Variation on Processor Performance. Asia-Pacific Computer Systems Architecture Conference 2004: 212-225 |
| c22 | | Tomoyuki Yamanaka, Vasily G. Moshnyaga: Reducing multiplier energy by data-driven voltage variation. ISCAS (2) 2004: 285-288 |
| c21 | | Vasily G. Moshnyaga, Koichi Masunaga, Naoki Kajiwara: A data reusing architecture for MPEG video coding. ISCAS (3) 2004: 797-800 |
| 2003 | ||
| j5 | | Vasily G. Moshnyaga: Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits. VLSI Signal Processing 33(1-2): 75-82 (2003) |
| c20 | | Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga: Reducing Access Count to Register-Files through Operand Reuse. Asia-Pacific Computer Systems Architecture Conference 2003: 112-121 |
| c19 | | Masayoshi Fujino, Vasily G. Moshnyaga: Dynamic operand transformation for low-power multiplier-accumulator design. ISCAS (5) 2003: 345-348 |
| 2002 | ||
| j4 | | Vasily G. Moshnyaga: Reducing energy dissipation of frame memory by adaptive bit-width compression. IEEE Trans. Circuits Syst. Video Techn. 12(8): 713-718 (2002) |
| c18 | | Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: Reducing power consumption of instruction ROMs by exploiting instruction frequency. APCCAS (2) 2002: 1-6 |
| c17 | | Jun-ni Ohban, Vasily G. Moshnyaga, Koji Inoue: Multiplier energy reduction through bypassing of partial products. APCCAS (2) 2002: 13-17 |
| c16 | | Vasily G. Moshnyaga: Reduction of memory accesses in motion estimation by block-data reuse. ICASSP 2002: 3128-3131 |
| c15 | | Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: A Low Energy Set-Associative I-Cache with Extended BTB. ICCD 2002: 187- |
| c14 | | Vasily G. Moshnyaga, Koji Inoue, Mizuka Fukagawa: Reducing energy consumption of video memory by bit-width compression. ISLPED 2002: 142-147 |
| c13 | | Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: A history-based I-cache for low-energy multimedia applications. ISLPED 2002: 148-153 |
| c12 | | Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints. PACS 2002: 18-32 |
| c11 | | Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga: Register File Energy Reduction by Operand Data Reuse. PATMOS 2002: 278-288 |
| 2001 | ||
| j3 | | Vasily G. Moshnyaga: A new computationally adaptive formulation of block-matching motion estimation. IEEE Trans. Circuits Syst. Video Techn. 11(1): 118-124 (2001) |
| c10 | | |
| c9 | | Vasily G. Moshnyaga, H. Tsuji: Cache energy reduction by dual voltage supply. ISCAS (4) 2001: 922-925 |
| c8 | | Vasily G. Moshnyaga: Energy reduction in queues and stacks by adaptive bitwidth compression. ISLPED 2001: 22-27 |
| 1999 | ||
| c7 | | Vasily G. Moshnyaga: A new architecture for computationally adaptive full-search block-matching motion estimation. ISCAS (4) 1999: 219-222 |
| c6 | | Vasily G. Moshnyaga: An MSB truncation scheme for low-power video processors. ISCAS (4) 1999: 291-294 |
| 1998 | ||
| j2 | | Vasily G. Moshnyaga, Naoto Watanabe, Keikichi Tamaru: A memory efficient array architecture for real-time motion estimation. Systems and Computers in Japan 29(9): 13-20 (1998) |
| 1997 | ||
| c5 | | Vasily G. Moshnyaga, Keikichi Tamaru: A Memory Efficient Array Architecture for Real-Time Motion Estimation. IPPS 1997: 28-32 |
| 1995 | ||
| j1 | | Vasily G. Moshnyaga, Yutaka Mori, Keikichi Tamaru: Register-Transfer Module Selection for Sub-Micron ASIC Design. IEICE Transactions 78-D(3): 252-255 (1995) |
| c4 | | Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru: A scheduling algorithm for synthesis of bus-partitioned architectures. ASP-DAC 1995 |
| c3 | | Vasily G. Moshnyaga, Keikichi Tamaru: A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers. ISCAS 1995: 1560-1563 |
| 1993 | ||
| c2 | | Vasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru: Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's. ICCAD 1993: 100-103 |
| 1992 | ||
| c1 | | Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura: Design of data-path module generators from algorithmic representations. Synthesis for Control Dominated Circuits 1992: 183-192 |
Colors in the list of coauthors
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