Takashi Morie

Takashi Morie, Takuji Miki, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho: A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise. ISSCC 2013: 272-273

Haichao Liang, Takashi Morie: A Motion Detection Model Inspired by the Neuronal Propagation in the Hippocampus. IEICE Transactions 95-A(2): 576-585 (2012)

Takuji Miki, Takashi Morie, Toshiaki Ozeki, Shiro Dosho: An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects. J. Solid-State Circuits 47(11): 2773-2782 (2012)

Shaohua Qian, Joo Kooi Tan, Hyoungseop Kim, Seiji Ishikawa, Takashi Morie: Obstacles Extraction Using a Moving Camera. ACCV Workshops (2) 2012: 441-453

Takashi Morie, Daisuke Atuti, Kazuki Ifuku, Yoshihiko Horio, Kazuyuki Aihara: A CMOS nonlinear-map circuit array for threshold-coupled chaotic maps using pulse-modulation approach. ECCTD 2011: 126-129

Frank L. Maldonado Huayaney, Hideki Tanaka, Takayuki Matsuo, Takashi Morie, Kazuyuki Aihara: A VLSI Spiking Neural Network with Symmetric STDP and Associative Memory Operation. ICONIP (3) 2011: 381-388

Haichao Liang, Takashi Morie: A Motion Detection Model Inspired by Hippocampal Function and Its FPGA Implementation. ICONIP (3) 2011: 522-529

Kenji Matsuzaka, Kazuki Nakada, Takashi Morie: Analog CMOS circuit implementation of a system of pulse-coupled oscillators for spike-based computation. ISCAS 2011: 2849-2852

Haichao Liang, Kazuki Nakada, Kenji Matsuzaka, Takashi Morie, Masato Okada: Parametric Control in a Region-Based Coupled MRF Model with Phase Dynamics for Coarse Image Region Segmentation. CSE 2010: 190-195

Takashi Morie, Yilai Sun, Haichao Liang, Makoto Igarashi, Chi-Hsien Huang, Seiji Samukawa: A 2-dimensional Si nanodisk array structure for spiking neuron models. ISCAS 2010: 781-784

Haichao Liang, Takashi Morie: Coarse Image Edge Detection using Self-adjusting Resistive-fuse Networks. PRIS 2010: 43-52

Ishtiaq Rasool Khan, Takashi Morie, Hiroyuki Miyamoto, Yasutaka Kuriya, Masaki Shimizu: Real-Time Human-Machine Interaction System Based on Face Authentication and Arm Posture Recognition. Brain-Inspired Information Technology 2010: 141-145

Takuji Kamada, Akitoshi Hanazawa, Takashi Morie: Shadow Elimination Mimicking the Human Visual System. Brain-Inspired Information Technology 2010: 147-151

Haichao Liang, Youhei Suzuki, Takashi Morie, Kazuki Nakada, Tsutomu Miki, Hatsuo Hayashi: An FPGA-Based Collision Warning System Using Moving-Object Detection Inspired by Neuronal Propagation in the Hippocampus. Brain-Inspired Information Technology 2010: 153-158

Daisuke Atuti, Takashi Morie, Kazuyuki Aihara: A Current-Sampling-Mode CMOS Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach. IEICE Transactions 92-A(5): 1308-1315 (2009)

Hideki Tanaka, Takashi Morie, Kazuyuki Aihara: A CMOS Spiking Neural Network Circuit with Symmetric/Asymmetric STDP Function. IEICE Transactions 92-A(7): 1690-1698 (2009)

Takashi Morie: Single-Electron Devices and Circuits Utilizing Stochastic Operation for Intelligent Information Processing. IJNMC 1(2): 1-28 (2009)

Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho: Design methods for pipeline & delta-sigma A-to-D converters with convex optimization. ASP-DAC 2009: 690-695

Yusuke Kawashima, Daisuke Atuti, Kazuki Nakada, Masato Okada, Takashi Morie: Coarse image region segmentation using region-and boundary-based coupled MRF models and their PWM VLSI implementation. IJCNN 2009: 1559-1565

Takashi Morie, Youngjae Kim: A subjective-contour generation LSI system with expandable pixel-parallel architecture for vision systems. ISSCC 2009: 478-479

Ken Okamoto, Toshio Watanabe, Akitoshi Hanazawa, Takashi Morie, Hiroshi Ban, Yuji Maeda: Video Monitoring of Slope Failure Using Spatiotemporal Gabor Filtering. SMC 2009: 960-965

Daisuke Atuti, Kazuki Nakada, Takashi Morie: CMOS pulse-modulation circuit implementation of phase-locked loop neural networks. ISCAS 2008: 2174-2177

Ishtiaq Rasool Khan, Hiroyuki Miyamoto, Takashi Morie: Face and arm-posture recognition for secure human-machine interaction. SMC 2008: 411-417

Shiro Dosho, Naoshi Yanagisawa, Kazuaki Sogawa, Yuji Yamada, Takashi Morie: An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter. IEICE Transactions 90-C(6): 1197-1202 (2007)

Haichao Liang, Takashi Morie, Youhei Suzuki, Kazuki Nakada, Tsutomu Miki, Hatsuo Hayashi: An FPGA-based CollisionWarning System Using Hybrid Approach. HIS 2007: 30-35

Osamu Nomura, Takashi Morie: Projection-Field-Type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach. ICONIP (1) 2007: 1081-1090

Shiro Dosho, Takashi Morie, Koji Okamoto, Yuji Yamada, Kazuaki Sogawa: A -90 dBc@ 10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit. IEICE Transactions 89-C(6): 739-745 (2006)

Osamu Nomura, Takashi Morie, Keisuke Korekado, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata: An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture. IEICE Transactions 89-C(6): 781-791 (2006)

Kan'ya Sasaki, Takashi Morie, Atsushi Iwata: A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory. IEICE Transactions 89-C(11): 1637-1644 (2006)

Daisuke Atuti, Takashi Morie, Kazuyuki Aihara: A Current-Sampling-Mode Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach Driven by Quantized Nonlinear Waveforms. APCCAS 2006: 1959-1963

Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata: A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations. ICNC (3) 2005: 1006-1014

Youngjae Kim, Takashi Morie: A pixel-parallel anisotropic diffusion algorithm for subjective contour generation. ISCAS (5) 2005: 4237-4240

Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata: A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture. Journal of Intelligent and Fuzzy Systems 15(3-4): 173-179 (2004)

Osamu Nomura, Takashi Morie, Keisuke Korekado, Masakazu Matsugu, Atsushi Iwata: A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition. KES 2004: 995-1001

Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata: A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture. KES 2003: 169-176

Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata: A cellular-automaton-type image extraction algorithm and its implementation using an FPGA. APCCAS (2) 2002: 197-200

Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata: Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. VLSI Design 2002: 71-76

Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata: Test circuits for substrate noise evaluation in CMOS digital ICs. ASP-DAC 2001: 13-14

Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata: Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. ISQED 2001: 482-487

Takashi Morie, Tomohiro Matsuura, Makoto Nagata, Atsushi Iwata: An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures. NIPS 2001: 1115-1122

Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata: Measurements and analyses of substrate noise waveform inmixed-signal IC environment. IEEE Trans. on CAD of Integrated Circuits and Systems 19(6): 671-678 (2000)

Noriaki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata: A smart imager for the vision processing front-END. ASP-DAC 2000: 19-20

Kenichi Murakoshi, Takashi Morie, Makoto Nagata, Atsushi Iwata: An arbitrary chaos generator core curcuit using PWM/PPM signals. ASP-DAC 2000: 23-24

Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie: A Feature Associative Processor for Image Recognition Based on A-D merged Architecture. VLSI 1999: 77-88

Souta Sakabayashi, Takashi Morie, Makoto Nagata, Atsushi Iwata: Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation. ICONIP 1998: 582-585

Hiroshi Ando, Takashi Morie, Makoto Nagata, Atsushi Iwata: Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method. ICONIP 1998: 586-589