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Prabhat Mishra
2010 – today
- 2013
[j30]Kanad Basu, Chetan Murthy, Prabhat Mishra: Bitmask aware compression of NISC control words. Integration 46(2): 131-141 (2013)- [j29]Kanad Basu, Prabhat Mishra: RATS: Restoration-Aware Trace Signal Selection for Post-Silicon Validation. IEEE Trans. VLSI Syst. 21(4): 605-613 (2013)
- [c60]Hadi Hajimiri, Prabhat Mishra, Swarup Bhunia: Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures. VLSI Design 2013: 49-54
- [c59]Kanad Basu, Prabhat Mishra, Priyadarsan Patra: Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults. VLSI Design 2013: 291-296
- [c58]Kamran Rahmani, Prabhat Mishra: Efficient Signal Selection Using Fine-grained Combination of Scan and Trace Buffers. VLSI Design 2013: 308-313
- [c57]Mingsong Chen, Prabhat Mishra: Assertion-Based Functional Consistency Checking between TLM and RTL Models. VLSI Design 2013: 320-325
- [c56]Prabhat Mishra, Masahiro Fujita, Virendra Singh, Nagesh Tamarapalli, Sharad Kumar, Rajesh Mittal: Tutorial T10: Post - Silicon Validation, Debug and Diagnosis. VLSI Design 2013
- 2012
- [j28]Xiaoke Qin, Weixun Wang, Prabhat Mishra: TCEC: Temperature and Energy-Constrained Scheduling in Real-Time Multitasking Systems. IEEE Trans. on CAD of Integrated Circuits and Systems 31(8): 1159-1168 (2012)
- [j27]Weixun Wang, Prabhat Mishra, Ann Gordon-Ross: Dynamic Cache Reconfiguration for Soft Real-Time Systems. ACM Trans. Embedded Comput. Syst. 11(2): 28 (2012)
- [j26]Mingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita: Automatic RTL Test Generation from SystemC TLM Specifications. ACM Trans. Embedded Comput. Syst. 11(2): 38 (2012)
- [j25]Xiaoke Qin, Prabhat Mishra: Directed test generation for validation of multicore architectures. ACM Trans. Design Autom. Electr. Syst. 17(3): 24 (2012)
- [j24]Weixun Wang, Prabhat Mishra: System-Wide Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking Systems. IEEE Trans. VLSI Syst. 20(5): 902-910 (2012)
- [c55]Xiaoke Qin, Prabhat Mishra: Automated generation of directed tests for transition coverage in cache coherence protocols. DATE 2012: 3-8
- [c54]Kamran Rahmani, Prabhat Mishra, Swarup Bhunia: Memory-based computing for performance and energy improvement in multicore architectures. ACM Great Lakes Symposium on VLSI 2012: 287-290
- [c53]Kamran Rahmani, Hadi Hajimiri, Kartik Shrivastava, Prabhat Mishra: Synergistic integration of code encryption and compression in embedded systems. ACM Great Lakes Symposium on VLSI 2012: 363-368
- [c52]Zhe Wang, Sanjay Ranka, Prabhat Mishra: Temperature-aware Task Partitioning for Real-Time Scheduling in Embedded Systems. VLSI Design 2012: 161-166
- [c51]
- 2011
- [j23]Prabhat Mishra, Zeljko Zilic, Sandeep K. Shukla: Guest Editors' Introduction: Multicore SoC Validation with Transaction-Level Models. IEEE Design & Test of Computers 28(3): 6-9 (2011)
- [j22]Zeljko Zilic, Prabhat Mishra, Sandeep K. Shukla: Challenges of Rapidly Emerging Consumer Space Multiprocessors. IEEE Design & Test of Computers 28(3): 52-53 (2011)
- [j21]Sandeep K. Shukla, Prabhat Mishra, Zeljko Zilic: A Brief History of Multiprocessors and EDA. IEEE Design & Test of Computers 28(3): 96 (2011)
- [j20]Weixun Wang, Prabhat Mishra: Dynamic Reconfiguration of Two-Level Cache Hierarchy in Real-Time Embedded Systems. J. Low Power Electronics 7(1): 17-28 (2011)
- [j19]Mingsong Chen, Prabhat Mishra: Property Learning Techniques for Efficient Generation of Directed Tests. IEEE Trans. Computers 60(6): 852-864 (2011)
- [j18]Xiaoke Qin, Chetan Muthry, Prabhat Mishra: Decoding-Aware Compression of FPGA Bitstreams. IEEE Trans. VLSI Syst. 19(3): 411-419 (2011)
- [c50]Weixun Wang, Prabhat Mishra, Sanjay Ranka: Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems. DAC 2011: 948-953
- [c49]Mingsong Chen, Prabhat Mishra: Decision ordering based property decomposition for functional test generation. DATE 2011: 167-172
- [c48]Hadi Hajimiri, Kamran Rahmani, Prabhat Mishra: Synergistic integration of dynamic cache reconfiguration and code compression in embedded systems. IGCC 2011: 1-8
- [c47]Xiaoke Qin, Prabhat Mishra: Efficient directed test generation for validation of multicore architectures. ISQED 2011: 276-283
- [c46]Kanad Basu, Prabhat Mishra, Priyadarsan Patra: Efficient combination of trace and scan signals for post silicon validation and debug. ITC 2011: 1-8
- [c45]Kartik Shrivastava, Prabhat Mishra: Dual Code Compression for Embedded Systems. VLSI Design 2011: 177-182
- [c44]Weixun Wang, Sanjay Ranka, Prabhat Mishra: A General Algorithm for Energy-Aware Dynamic Reconfiguration in Multitasking Systems. VLSI Design 2011: 334-339
- [c43]Kanad Basu, Prabhat Mishra: Efficient Trace Signal Selection for Post Silicon Validation and Debug. VLSI Design 2011: 352-357
- [c42]Kanad Basu, Prabhat Mishra: Efficient trace data compression using statically selected dictionary. VTS 2011: 14-19
- 2010
- [j17]Mingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita: Efficient test case generation for validation of UML activity diagrams. Design Autom. for Emb. Sys. 14(2): 105-130 (2010)
- [j16]
- [j15]Mingsong Chen, Prabhat Mishra: Functional Test Generation Using Efficient Property Clustering and Learning Techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 396-404 (2010)
- [j14]Kanad Basu, Prabhat Mishra: Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods. IEEE Trans. VLSI Syst. 18(9): 1277-1286 (2010)
- [c41]Weixun Wang, Prabhat Mishra: PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme. DAC 2010: 705-710
- [c40]Mingsong Chen, Xiaoke Qin, Prabhat Mishra: Efficient decision ordering techniques for SAT-based test generation. DATE 2010: 490-495
- [c39]Weixun Wang, Xiaoke Qin, Prabhat Mishra: Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach. ISLPED 2010: 85-90
- [c38]Xiaoke Qin, Mingsong Chen, Prabhat Mishra: Synchronized Generation of Directed Tests Using Satisfiability Solving. VLSI Design 2010: 351-356
- [c37]Weixun Wang, Prabhat Mishra: Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems. VLSI Design 2010: 357-362
- [e2]Sanjay Ranka, Arunava Banerjee, Kanad Kishore Biswas, Sumeet Dua, Prabhat Mishra, Rajat Moona, Sheung-Hung Poon, Cho-Li Wang (Eds.): Contemporary Computing - Third International Conference, IC3 2010, Noida, India, August 9-11, 2010. Proceedings, Part I. Communications in Computer and Information Science 94, Springer 2010, ISBN 978-3-642-14833-0
- [e1]Sanjay Ranka, Arunava Banerjee, Kanad Kishore Biswas, Sumeet Dua, Prabhat Mishra, Rajat Moona, Sheung-Hung Poon, Cho-Li Wang (Eds.): Contemporary Computing - Third International Conference, IC3 2010, Noida, India, August 9-11, 2010, Proceedings, Part II. Communications in Computer and Information Science 95, Springer 2010, ISBN 978-3-642-14824-8
2000 – 2009
- 2009
- [j13]Prabhat Mishra: Guest Editor Introduction: Special Issue on Nano/Bio-Inspired Applications and Architectures. International Journal of Parallel Programming 37(4): 343-344 (2009)
- [j12]Xiaoke Qin, Prabhat Mishra: A Universal Placement Technique of Compressed Instructions for Efficient Parallel Decompression. IEEE Trans. on CAD of Integrated Circuits and Systems 28(8): 1224-1236 (2009)
- [j11]Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt: Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation. ACM Trans. Embedded Comput. Syst. 8(3) (2009)
- [j10]Heon-Mo Koo, Prabhat Mishra: Functional test generation using design and property decomposition techniques. ACM Trans. Embedded Comput. Syst. 8(4) (2009)
- [c36]Thanh Nga Dang, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra: Generating test programs to cover pipeline interactions. DAC 2009: 142-147
- [c35]Chetan Murthy, Prabhat Mishra: Bitmask-based control word compression for NISC architectures. ACM Great Lakes Symposium on VLSI 2009: 321-326
- [c34]
- [c33]Weixun Wang, Prabhat Mishra: Dynamic Reconfiguration of Two-Level Caches in Soft Real-Time Embedded Systems. ISVLSI 2009: 145-150
- [c32]Chetan Murthy, Prabhat Mishra: Lossless Compression Using Efficient Encoding of Bitmasks. ISVLSI 2009: 163-168
- [c31]Prabhat Mishra, Mingsong Chen: Efficient Techniques for Directed Test Generation Using Incremental Satisfiability. VLSI Design 2009: 65-70
- [c30]Xiaoke Qin, Prabhat Mishra: Efficient Placement of Compressed Code for Parallel Decompression. VLSI Design 2009: 335-340
- [c29]Weixun Wang, Prabhat Mishra, Ann Gordon-Ross: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems. VLSI Design 2009: 547-552
- 2008
- [j9]Seok-Won Seong, Prabhat Mishra: Bitmask-Based Code Compression for Embedded Systems. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 673-685 (2008)
- [j8]Prabhat Mishra, Nikil Dutt: Specification-driven directed test generation for validation of pipelined processors. ACM Trans. Design Autom. Electr. Syst. 13(3) (2008)
- [c28]Heon-Mo Koo, Prabhat Mishra: Specification-based compaction of directed tests for functional validation of pipelined processors. CODES+ISSS 2008: 137-142
- [c27]Kanad Basu, Prabhat Mishra: A novel test-data compression technique using application-aware bitmask and dictionary selection methods. ACM Great Lakes Symposium on VLSI 2008: 83-88
- [c26]Mingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita: Coverage-driven automatic test generation for uml activity diagrams. ACM Great Lakes Symposium on VLSI 2008: 139-142
- 2007
- [c25]Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra, Xu Cheng: A Retargetable Software Timing Analyzer Using Architecture Description Language. ASP-DAC 2007: 396-401
- [c24]Seok-Won Seong, Prabhat Mishra: An efficient code compression technique using application-aware bitmask and dictionary selection methods. DATE 2007: 582-587
- [c23]Mingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita: Towards RTL test generation from SystemC TLM specifications. HLDVT 2007: 91-96
- 2006
- [j7]Mehrdad Reshadi, Nikil Dutt, Prabhat Mishra: A retargetable framework for instruction-set architecture simulation. ACM Trans. Embedded Comput. Syst. 5(2): 431-452 (2006)
- [j6]Prabhat Mishra, Aviral Shrivastava, Nikil Dutt: Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs. ACM Trans. Design Autom. Electr. Syst. 11(3): 626-658 (2006)
- [c22]Heon-Mo Koo, Prabhat Mishra: Functional test generation using property decompositions for validation of pipelined processors. DATE 2006: 1240-1245
- [c21]Heon-Mo Koo, Prabhat Mishra: Test generation using SAT-based bounded model checking for validation of pipelined processors. ACM Great Lakes Symposium on VLSI 2006: 362-365
- [c20]Seok-Won Seong, Prabhat Mishra: A bitmask-based code compression technique for embedded systems. ICCAD 2006: 251-254
- [c19]Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir: Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. MTV 2006: 33-36
- 2005
- [b1]Prabhat Mishra, Nikil D. Dutt: Functional verification of programmable embedded architectures - a top-down approach. Springer 2005, ISBN 978-0-387-26143-0, pp. I-XVIII, 1-180
- [j5]Prabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir: A methodology for validation of microprocessors using symbolic simulation. IJES 1(1/2): 14-22 (2005)
- [c18]Mehrdad Reshadi, Prabhat Mishra: Memory access optimizations in instruction-set simulators. CODES+ISSS 2005: 237-242
- [c17]Prabhat Mishra, Nikil D. Dutt: Functional Coverage Driven Test Generation for Validation of Pipelined Processors. DATE 2005: 678-683
- [c16]Prabhat Mishra, Heon-Mo Koo, Zhuo Huang: Language-driven Validation of Pipelined Processors using Satisfiability Solvers. MTV 2005: 119-126
- 2004
- [j4]Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, Magdy S. Abadir: A Top-Down Methodology for Microprocessor Validation. IEEE Design & Test of Computers 21(2): 122-131 (2004)
- [j3]Prabhat Mishra, Nikil Dutt: Modeling and validation of pipeline specifications. ACM Trans. Embedded Comput. Syst. 3(1): 114-139 (2004)
- [j2]Prabhat Mishra, Mahesh Mamidipaka, Nikil Dutt: Processor-memory coexploration using an architecture description language. ACM Trans. Embedded Comput. Syst. 3(1): 140-162 (2004)
- [c15]Prabhat Mishra, Nikil Dutt: Graph-Based Functional Test Program Generation for Pipelined Processors. DATE 2004: 182-187
- [c14]
- [c13]Prabhat Mishra, Nikil D. Dutt, Yaron Kashai: Functional Verification of Pipelined Processors: A Case Study. MTV 2004: 79-84
- [c12]Prabhat Mishra, Arun Kejariwal, Nikil Dutt: Synthesis-driven Exploration of Pipelined Embedded Processors. VLSI Design 2004: 921-926
- 2003
- [j1]Prabhat Mishra, Nikil Dutt, Hiroyuki Tomiyama: Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications. Design Autom. for Emb. Sys. 8(2-3): 249-265 (2003)
- [c11]Mehrdad Reshadi, Nikhil Bansal, Prabhat Mishra, Nikil D. Dutt: An efficient retargetable framework for instruction-set simulation. CODES+ISSS 2003: 13-18
- [c10]Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt: Instruction set compiled simulation: a technique for fast and flexible instruction set simulation. DAC 2003: 758-763
- [c9]Prabhat Mishra, Nikil D. Dutt: A Methodology for Validation of Microprocessors using Equivalence Checking. MTV 2003: 83-88
- [c8]Prabhat Mishra, Arun Kejariwal, Nikil Dutt: Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models. IEEE International Workshop on Rapid System Prototyping 2003: 226-232
- 2002
- [c7]Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama: Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. DATE 2002: 36-43
- [c6]Prabhat Mishra, Nikil Dutt: Automatic functional test program generation for pipelined processors using model checking. HLDVT 2002: 99-103
- [c5]Prabhat Mishra, Nikil D. Dutt: Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions. DIPES 2002: 81-90
- [c4]Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language. VLSI Design 2002: 458-
- 2001
- [c3]Prabhat Mishra, Nikil Dutt, Alex Nicolau: Automatic validation of pipeline specifications. HLDVT 2001: 9-13
- [c2]Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau: Functional abstraction driven design space exploration of heterogeneous programmable architectures. ISSS 2001: 256-261
- [c1]Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language. VLSI Design 2001: 70-75
Coauthor Index
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last updated on 2013-10-02 11:19 CEST by the dblp team