Renate Merker

Markus Rullmann, Renate Merker: A Cost Model for Partial Dynamic Reconfiguration. T. HiPEAC 4: 370-390 (2011)

Markus Rullmann, Renate Merker: Design Methods and Tools for Improved Partial Dynamic Reconfiguration. Dynamically Reconfigurable Systems 2010: 161-181

Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred Glesner: An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs. FPL 2009: 92-98

Rainer Schaffer, Renate Merker, Frank Hannig, Jürgen Teich: Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. DSD 2008: 391-398

Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker: Fine grain reconfigurable architectures. FPL 2008: 348

Markus Rullmann, Renate Merker: Synthesis of efficiently reconfigurable datapaths for reconfigurable computing. FPT 2008: 277-280

Markus Rullmann, Renate Merker: A cost model for partial dynamic reconfiguration. ICSAMOS 2008: 182-186

Markus Rullmann, Renate Merker: A Reconfiguration Aware Circuit Mapper for FPGAs. IPDPS 2007: 1-8

Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier: Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC 2007: 61-68

Markus Rullmann, Renate Merker: Design and Implementation of Reconfigurable Tasks with Minimum Reconfiguration Overhead. ARCS Workshops 2006: 132-141

Sebastian Siegel, Renate Merker: Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy. ASAP 2006: 28-32

Sebastian Siegel, Renate Merker: Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource Constraints. Euro-Par 2006: 1181-1191

Markus Rullmann, Renate Merker: Maximum edge matching for reconfigurable computing. IPDPS 2006

Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Renate Merker: An Architecture Description Language for Massively Parallel Processor Architectures. MBMV 2006: 11-20

Rainer Schaffer, Renate Merker, Francky Catthoor: Derivation of Packing Instructions for Exploiting Sub-Word Parallelism. PARELEC 2006: 167-172

Sebastian Siegel, Rainer Schaffer, Renate Merker: Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels. PARELEC 2006: 173-180

Rainer Schaffer, Renate Merker: Parameterized Mapping of Algorithms onto Processor Arrays with Sub-Word Parallelism. ICSAMOS 2006: 99-106

Markus Rullmann, Sebastian Siegel, Renate Merker: Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching. IPDPS 2005

Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys: Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC 2005: 27-34

Jan Müller, Dirk Fimmel, Renate Merker: Exploitation of Instruction-Level Parallelism for Optimal Loop Scheduling. Interaction between Compilers and Computer Architectures 2004: 13-21

Sebastian Siegel, Renate Merker: Optimized Data-Reuse in Processor Arrays. ASAP 2004: 315-325

Jan Müller, Dirk Fimmel, Renate Merker: Optimal Loop Scheduling with Register Constraints Using Flow Graphs. ISPAN 2004: 180-186

Sebastian Siegel, Renate Merker: Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays. PARELEC 2004: 85-90

Mathias Kortke, Jan Müller, Rainer Schaffer, Sebastian Siegel, Renate Merker, Jürgen Kelber: A Parallel Hardware-Software System for Signal Processing Algorithms. PARELEC 2004: 215-220

Jan Müller, Dirk Fimmel, Renate Merker, Rainer Schaffer: A Hardware-Software System for Tomographic Reconstruction. Journal of Circuits, Systems, and Computers 12(2): 203- (2003)

Rainer Schaffer, Renate Merker, Francky Catthoor: Causality Constraints for Processor Architectures with Sub-Word Parallelism. DSD 2003: 82-89

Rainer Schaffer, Renate Merker, Francky Catthoor: Systematic Design of Programs with Sub-Word Parallelism. PARELEC 2002: 393-398

Dirk Fimmel, Renate Merker: Design of Processor Arrays for Reconfigurable Architectures. The Journal of Supercomputing 19(1): 41-56 (2001)

Rainer Schaffer, Francky Catthoor, Renate Merker: Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel. Parallel Algorithms Appl. 15(3-4): 201-228 (2000)

Renate Merker: High-Level Synthesis System (HLDESA) for Processor Arrays. PARELEC 2000: 89-93

Mathias Kortke, Thomas Schmitt, Renate Merker: Application of Partitioning Methods for the Design of Parallel Programs for a System of Digital Signal Processors. PARELEC 2000: 139-143

Rainer Schaffer, Renate Merker, Francky Catthoor: Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel. VLSI Design 2000: 104-109

Uwe Eckhardt, Renate Merker: Hierarchical algorithm partitioning at system level for an improved utilization of memory structures. IEEE Trans. on CAD of Integrated Circuits and Systems 18(1): 14-24 (1999)

Thomas Schmitt, Dirk Fimmel, Mathias Kortke, Renate Merker: Parallel Processor Array for Tomographic Reconstruction Algorithms. EUROCAST 1999: 127-141

Mathias Kortke, Dirk Fimmel, Renate Merker: Parallelization of Algorithms for a System of Digital Signal Processors. EUROMICRO 1999: 1046-1050

Dirk Fimmel, Renate Merker: Localization of Data Transfer in Processor Arrays. Euro-Par 1999: 401-408

Dirk Fimmel, Renate Merker: Design of Processor Arrays for Real-Time Applications. Euro-Par 1998: 1018-1028

Dirk Fimmel, Renate Merker: Determination of the Processor Functionality in the Design of Processor Arrays. ASAP 1997: 199-208

Uwe Eckhardt, Renate Merker: Scheduling in Co-Partitioned Array Architectures. ASAP 1997: 219-228

Renate Merker, Ulrich Eckhardt, Dirk Fimmel, H. Schreiber: A System for Designing Parallel Processor Arrays. EUROCAST 1997: 3-12

Uwe Eckhardt, Renate Merker: Optimization of the Background Memory Utilization by Partitioning. ISSS 1997: 82-89

Dirk Fimmel, Renate Merker: Propagation of I/O-Variables in Massively Parallel Processor Arrays. PDP 1996: 501-509

A. Schubert, Renate Merker, H. Schreiber: Systematic Generation of a Variety of Processor Arrays. Parcella 1994: 267-276