DBLP: Jimson Mathew

	2013
c45		Xiaoyu Huang, Jimson Mathew, Rishad A. Shafik, Subhasis Bhattacharjee, Dhiraj K. Pradhan: A fast and Effective DFT for test and diagnosis of power switches in SoCs. DATE 2013: 1089-1092
	2012
j18		Luo Sun, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits. J. Low Power Electronics 8(3): 270-282 (2012)
c44		Pranav Yeolekar, Rishad A. Shafik, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: STEP: a unified design methodology for secure test and IP core protection. ACM Great Lakes Symposium on VLSI 2012: 333-338
c43		Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Saraju P. Mohanty: Low complexity cross parity codes for multiple and random bit error correction. ISQED 2012: 57-62
c42		Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Saraju P. Mohanty: An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies. ISVLSI 2012: 141-146
c41		Rishad A. Shafik, Bashir M. Al-Hashimi, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework. ISVLSI 2012: 189-194
c40		Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases. VDAT 2012: 258-269
	2011
j17		Vishram Mishra, Jimson Mathew, Dhiraj K. Pradhan: Fault-tolerant de-Bruijn graph based multipurpose architecture and routing protocol for wireless sensor networks. IJSNet 10(3): 160-175 (2011)
j16		Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski: A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. J. Low Power Electronics 7(4): 471-481 (2011)
j15		Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan: Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. IEEE Trans. VLSI Syst. 19(8): 1469-1480 (2011)
j14		Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Bhargab B. Bhattacharya, Saraju P. Mohanty: A Routing-Aware ILS Design Technique. IEEE Trans. VLSI Syst. 19(12): 2335-2338 (2011)
j13		Babita R. Jose, Jimson Mathew, P. Mythili: A Multi-Mode Sigma-Delta ADC for GSM/WCDMA/WLAN Applications. Signal Processing Systems 62(2): 117-130 (2011)
c39		Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields. ECCTD 2011: 600-603
c38		Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan, Saraju P. Mohanty: BCH code based multiple bit error correction in finite field multiplier circuits. ISQED 2011: 615-620
c37		S. Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski: Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization. VLSI Design 2011: 304-309
	2010
j12		Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan: Secure Testable S-box Architecture for Cryptographic Hardware Implementation. Comput. J. 53(5): 581-591 (2010)
j11		Jimson Mathew, Abusaleh M. Jabir, Ashutosh Kumar Singh, Hafizur Rahaman, Dhiraj K. Pradhan: A Galois field-based logic synthesis with testability. IET Computers & Digital Techniques 4(4): 263-273 (2010)
j10		Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: Simplified bit parallel systolic multipliers for special class of galois field (2^m) with testability. IET Computers & Digital Techniques 4(5): 428-437 (2010)
j9		Somsubhra Talapatra, Hafizur Rahaman, Jimson Mathew: Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of GF(2^m). IEEE Trans. VLSI Syst. 18(5): 847-852 (2010)
j8		Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan: Test Generation in Systolic Architecture for Multiplication Over GF(2 ^m). IEEE Trans. VLSI Syst. 18(9): 1366-1371 (2010)
c36		Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir, Saraju P. Mohanty, Dhiraj K. Pradhan: On the design of different concurrent EDC schemes for S-Box and GF(p). ISQED 2010: 211-218
c35		Savita Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: Layout-aware Illinois Scan design for high fault coverage coverage. ISQED 2010: 683-688
c34		Anas Abu Taleb, Jimson Mathew, Dhiraj K. Pradhan: Fault diagnosis in multi layered De Bruijn based architectures for sensor networks. PerCom Workshops 2010: 456-461
c33		Jimson Mathew, Savita Banerjee, Hafizur Rahaman, Dhiraj K. Pradhan, Saraju P. Mohanty, Abusaleh M. Jabir: On the synthesis of attack tolerant cryptographic hardware. VLSI-SoC 2010: 286-291
	2009
j7		Jimson Mathew, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan: Single error correctable bit parallel multipliers over GF(2^m). IET Computers & Digital Techniques 3(3): 281-288 (2009)
j6		Dmitri Maslov, Jimson Mathew, Donny Cheung, Dhiraj K. Pradhan: An O(m²)-depth quantum algorithm for the elliptic curve discrete logarithm problem over GF(2^m)^a. Quantum Information & Computation 9(7): 610-621 (2009)
c32		Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty, Jimson Mathew: Single ended 6T SRAM with isolated read-port for low-power embedded systems. DATE 2009: 917-922
c31		Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: C-testable S-box implementation for secure advanced encryption standard. IOLTS 2009: 210-211
c30		Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan: Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. VLSI Design 2009: 307-312
	2008
j5		Babita R. Jose, P. Mythili, Jimson Mathew: GA-based Optimization of Sigma-delta Modulators for Wireless Transceivers. Engineering Letters 16(4): 473-479 (2008)
j4		Jimson Mathew, R. Mahesh, A. Prasad Vinod, Edmund Ming-Kit Lai: Realization of Low Power High-Speed Channel Filters with Stringent Adjacent Channel Attenuation Specifications for Wireless Communication Receivers. IEICE Transactions 91-A(9): 2564-2570 (2008)
j3		Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir: Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m). IEEE Trans. Computers 57(9): 1289-1294 (2008)
j2		Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew: GfXpress: A Technique for Synthesis and Optimization of GF(2^m) Polynomials. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 698-711 (2008)
j1		Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir: C-testable bit parallel multipliers over GF(2^m). ACM Trans. Design Autom. Electr. Syst. 13(1) (2008)
c29		Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan: De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. DATE 2008: 1370-1373
c28		Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection. IOLTS 2008: 16-21
c27		Jimson Mathew, Jawar Singh, Anas Abu Taleb, Dhiraj K. Pradhan: Fault Tolerant Reversible Finite Field Arithmetic Circuits. IOLTS 2008: 188-189
c26		Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan: Fault tolerant bit parallel finite field multipliers using LDPC codes. ISCAS 2008: 1684-1687
c25		Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan: A nano-CMOS process variation induced read failure tolerant SRAM cell. ISCAS 2008: 3334-3337
c24		Renji Remesan, Muhammad A. Shamim, Dawei Han, Jimson Mathew: ANFIS and NNARX based rainfall-runoff modeling. SMC 2008: 1454-1459
c23		Babita Roslind Jose, P. Mythili, Jimson Mathew, Renji Remesan: GA-based optimization of a fourth-order sigma-delta modulator for WLAN. SMC 2008: 1460-1464
c22		Yi Xin Su, Jimson Mathew, Jawar Singh, Dhiraj K. Pradhan: Pseudo parallel architecture for AES with error correction. SoCC 2008: 187-190
c21		Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. SoCC 2008: 243-246
c20		Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: Failure analysis for ultra low power nano-CMOS SRAM under process variations. SoCC 2008: 251-254
c19		Donny Cheung, Dmitri Maslov, Jimson Mathew, Dhiraj K. Pradhan: On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography. TQC 2008: 96-104
c18		Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan: Single Error Correcting Finite Field Multipliers Over GF(2m). VLSI Design 2008: 33-38
c17		Jimson Mathew, Hafizur Rahaman, Babita R. Jose, Dhiraj K. Pradhan: Design of Reversible Finite Field Arithmetic Circuits with Error Detection. VLSI Design 2008: 453-459
c16		Jimson Mathew, Hafizur Rahaman, Ashutosh Kumar Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan: A Galois Field Based Logic Synthesis Approach with Testability. VLSI Design 2008: 629-634
	2007
c15		Jawar Singh, Jimson Mathew, Mohammad Hosseinabady, Dhiraj K. Pradhan: Single Event Upset Detection and Correction. ICIT 2007: 13-18
c14		Babita R. Jose, P. Mythili, Jawar Singh, Jimson Mathew: A Triple-Mode Sigma-Delta Modulator Design for Wireless Standards. ICIT 2007: 127-132
c13		Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan: Reliable network-on-chip based on generalized de Bruijn graph. HLDVT 2007: 3-10
c12		Jimson Mathew, Hafizur Rahaman, Dhiraj K. Pradhan: Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set. IOLTS 2007: 207-208
c11		Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew: Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. ISCAS 2007: 141-144
c10		R. Stapenhurst, K. Maharatna, Jimson Mathew, José L. Núñez-Yáñez, Dhiraj K. Pradhan: On the Hardware Reduction of z-Datapath of Vectoring CORDIC. ISCAS 2007: 3002-3005
c9		Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew: CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. ISCAS 2007: 3675-3678
c8		Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew: SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs. ISQED 2007: 380-385
c7		Babita R. Jose, Jimson Mathew, P. Mythili, Dhiraj K. Pradhan: A triple-mode feed-forward sigma-delta modulator design for GSM / WCDMA / WLAN applications. SoCC 2007: 309-312
c6		Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan: Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). VLSI Design 2007: 479-484
c5		Hafizur Rahaman, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan: Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). VTS 2007: 422-430
	2006
c4		Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: Easily Testable Implementation for Bit Parallel Multipliers in GF (2m). HLDVT 2006: 48-54
c3		Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew: An efficient technique for synthesis and optimization of polynomials in GF(2^m). ICCAD 2006: 151-157
	2002
c2		Jimson Mathew, Elena Dubrova: Self-Checking 1-out-of-n CMOS Current-Mode Checker. DFT 2002: 69-77
	1999
c1		Jimson Mathew, D. Radhakrishnan, T. Srikanthan: Residue-to-binary arithmetic converter for moduli set {2n -1, 2n, 2n+1, 2n+1 -1}. NSIP 1999: 185-188

2013

c45

Xiaoyu Huang, Jimson Mathew, Rishad A. Shafik, Subhasis Bhattacharjee, Dhiraj K. Pradhan: A fast and Effective DFT for test and diagnosis of power switches in SoCs. DATE 2013: 1089-1092

2012

j18

Luo Sun, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits. J. Low Power Electronics 8(3): 270-282 (2012)

c44

Pranav Yeolekar, Rishad A. Shafik, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: STEP: a unified design methodology for secure test and IP core protection. ACM Great Lakes Symposium on VLSI 2012: 333-338

c43

Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Saraju P. Mohanty: Low complexity cross parity codes for multiple and random bit error correction. ISQED 2012: 57-62

c42

Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Saraju P. Mohanty: An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies. ISVLSI 2012: 141-146

c41

Rishad A. Shafik, Bashir M. Al-Hashimi, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework. ISVLSI 2012: 189-194

c40

Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases. VDAT 2012: 258-269

2011

j17

Vishram Mishra, Jimson Mathew, Dhiraj K. Pradhan: Fault-tolerant de-Bruijn graph based multipurpose architecture and routing protocol for wireless sensor networks. IJSNet 10(3): 160-175 (2011)

j16

Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski: A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. J. Low Power Electronics 7(4): 471-481 (2011)

j15

Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan: Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. IEEE Trans. VLSI Syst. 19(8): 1469-1480 (2011)

j14

Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Bhargab B. Bhattacharya, Saraju P. Mohanty: A Routing-Aware ILS Design Technique. IEEE Trans. VLSI Syst. 19(12): 2335-2338 (2011)

j13

Babita R. Jose, Jimson Mathew, P. Mythili: A Multi-Mode Sigma-Delta ADC for GSM/WCDMA/WLAN Applications. Signal Processing Systems 62(2): 117-130 (2011)

c39

Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields. ECCTD 2011: 600-603

c38

Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan, Saraju P. Mohanty: BCH code based multiple bit error correction in finite field multiplier circuits. ISQED 2011: 615-620

c37

S. Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski: Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization. VLSI Design 2011: 304-309

2010

j12

Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan: Secure Testable S-box Architecture for Cryptographic Hardware Implementation. Comput. J. 53(5): 581-591 (2010)

j11

Jimson Mathew, Abusaleh M. Jabir, Ashutosh Kumar Singh, Hafizur Rahaman, Dhiraj K. Pradhan: A Galois field-based logic synthesis with testability. IET Computers & Digital Techniques 4(4): 263-273 (2010)

j10

Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: Simplified bit parallel systolic multipliers for special class of galois field (2^m) with testability. IET Computers & Digital Techniques 4(5): 428-437 (2010)

Somsubhra Talapatra, Hafizur Rahaman, Jimson Mathew: Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of GF(2^m). IEEE Trans. VLSI Syst. 18(5): 847-852 (2010)

Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan: Test Generation in Systolic Architecture for Multiplication Over GF(2 ^m). IEEE Trans. VLSI Syst. 18(9): 1366-1371 (2010)

c36

Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir, Saraju P. Mohanty, Dhiraj K. Pradhan: On the design of different concurrent EDC schemes for S-Box and GF(p). ISQED 2010: 211-218

c35

Savita Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: Layout-aware Illinois Scan design for high fault coverage coverage. ISQED 2010: 683-688

c34

Anas Abu Taleb, Jimson Mathew, Dhiraj K. Pradhan: Fault diagnosis in multi layered De Bruijn based architectures for sensor networks. PerCom Workshops 2010: 456-461

c33

Jimson Mathew, Savita Banerjee, Hafizur Rahaman, Dhiraj K. Pradhan, Saraju P. Mohanty, Abusaleh M. Jabir: On the synthesis of attack tolerant cryptographic hardware. VLSI-SoC 2010: 286-291

2009

Jimson Mathew, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan: Single error correctable bit parallel multipliers over GF(2^m). IET Computers & Digital Techniques 3(3): 281-288 (2009)

Dmitri Maslov, Jimson Mathew, Donny Cheung, Dhiraj K. Pradhan: An O(m²)-depth quantum algorithm for the elliptic curve discrete logarithm problem over GF(2^m)^a. Quantum Information & Computation 9(7): 610-621 (2009)

c32

Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty, Jimson Mathew: Single ended 6T SRAM with isolated read-port for low-power embedded systems. DATE 2009: 917-922

c31

Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: C-testable S-box implementation for secure advanced encryption standard. IOLTS 2009: 210-211

c30

Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan: Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. VLSI Design 2009: 307-312

2008

Babita R. Jose, P. Mythili, Jimson Mathew: GA-based Optimization of Sigma-delta Modulators for Wireless Transceivers. Engineering Letters 16(4): 473-479 (2008)

Jimson Mathew, R. Mahesh, A. Prasad Vinod, Edmund Ming-Kit Lai: Realization of Low Power High-Speed Channel Filters with Stringent Adjacent Channel Attenuation Specifications for Wireless Communication Receivers. IEICE Transactions 91-A(9): 2564-2570 (2008)

Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir: Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m). IEEE Trans. Computers 57(9): 1289-1294 (2008)

Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew: GfXpress: A Technique for Synthesis and Optimization of GF(2^m) Polynomials. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 698-711 (2008)

Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir: C-testable bit parallel multipliers over GF(2^m). ACM Trans. Design Autom. Electr. Syst. 13(1) (2008)

c29

Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan: De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. DATE 2008: 1370-1373

c28

Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection. IOLTS 2008: 16-21

c27

Jimson Mathew, Jawar Singh, Anas Abu Taleb, Dhiraj K. Pradhan: Fault Tolerant Reversible Finite Field Arithmetic Circuits. IOLTS 2008: 188-189

c26

Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan: Fault tolerant bit parallel finite field multipliers using LDPC codes. ISCAS 2008: 1684-1687

c25

Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan: A nano-CMOS process variation induced read failure tolerant SRAM cell. ISCAS 2008: 3334-3337

c24

Renji Remesan, Muhammad A. Shamim, Dawei Han, Jimson Mathew: ANFIS and NNARX based rainfall-runoff modeling. SMC 2008: 1454-1459

c23

Babita Roslind Jose, P. Mythili, Jimson Mathew, Renji Remesan: GA-based optimization of a fourth-order sigma-delta modulator for WLAN. SMC 2008: 1460-1464

c22

Yi Xin Su, Jimson Mathew, Jawar Singh, Dhiraj K. Pradhan: Pseudo parallel architecture for AES with error correction. SoCC 2008: 187-190

c21

Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. SoCC 2008: 243-246

c20

Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: Failure analysis for ultra low power nano-CMOS SRAM under process variations. SoCC 2008: 251-254

c19

Donny Cheung, Dmitri Maslov, Jimson Mathew, Dhiraj K. Pradhan: On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography. TQC 2008: 96-104

c18

Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan: Single Error Correcting Finite Field Multipliers Over GF(2m). VLSI Design 2008: 33-38

c17

Jimson Mathew, Hafizur Rahaman, Babita R. Jose, Dhiraj K. Pradhan: Design of Reversible Finite Field Arithmetic Circuits with Error Detection. VLSI Design 2008: 453-459

c16

Jimson Mathew, Hafizur Rahaman, Ashutosh Kumar Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan: A Galois Field Based Logic Synthesis Approach with Testability. VLSI Design 2008: 629-634

2007

c15

Jawar Singh, Jimson Mathew, Mohammad Hosseinabady, Dhiraj K. Pradhan: Single Event Upset Detection and Correction. ICIT 2007: 13-18

c14

Babita R. Jose, P. Mythili, Jawar Singh, Jimson Mathew: A Triple-Mode Sigma-Delta Modulator Design for Wireless Standards. ICIT 2007: 127-132

c13

Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan: Reliable network-on-chip based on generalized de Bruijn graph. HLDVT 2007: 3-10

c12

Jimson Mathew, Hafizur Rahaman, Dhiraj K. Pradhan: Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set. IOLTS 2007: 207-208

c11

Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew: Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. ISCAS 2007: 141-144

c10

R. Stapenhurst, K. Maharatna, Jimson Mathew, José L. Núñez-Yáñez, Dhiraj K. Pradhan: On the Hardware Reduction of z-Datapath of Vectoring CORDIC. ISCAS 2007: 3002-3005

Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew: CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. ISCAS 2007: 3675-3678

Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew: SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs. ISQED 2007: 380-385

Babita R. Jose, Jimson Mathew, P. Mythili, Dhiraj K. Pradhan: A triple-mode feed-forward sigma-delta modulator design for GSM / WCDMA / WLAN applications. SoCC 2007: 309-312

Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan: Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). VLSI Design 2007: 479-484

Hafizur Rahaman, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan: Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). VTS 2007: 422-430

2006

Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan: Easily Testable Implementation for Bit Parallel Multipliers in GF (2m). HLDVT 2006: 48-54

Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew: An efficient technique for synthesis and optimization of polynomials in GF(2^m). ICCAD 2006: 151-157

2002

Jimson Mathew, Elena Dubrova: Self-Checking 1-out-of-n CMOS Current-Mode Checker. DFT 2002: 69-77

1999

Jimson Mathew, D. Radhakrishnan, T. Srikanthan: Residue-to-binary arithmetic converter for moduli set {2n -1, 2n, 2n+1, 2n+1 -1}. NSIP 1999: 185-188

1	Bashir M. Al-Hashimi	[c41]
2	Costas Argyrides	[c18]
3	S. Banerjee	[c37]
4	Savita Banerjee	[c35] [c33]
5	Shibaji Banerjee	[j16] [j14]
6	Subhasis Bhattacharjee	[c45]
7	Bhargab B. Bhattacharya	[j14]
8	Donny Cheung	[j6] [c19]
9	Maciej J. Ciesielski	[j16] [c37]
10	Elena Dubrova	[c2]
11	Dawei Han	[c24]
12	Simon Hollis	[c32]
13	Mohammad Hosseinabady	[j15] [c29] [c26] [c15] [c13]
14	Xiaoyu Huang	[c45]
15	Abusaleh M. Jabir	[c43] [c42] [c40] [c39] [c38] [j11] [j10] [c36] [c33] [j7] [c31] [j3] [j2] [j1] [c28] [c26] [c18] [c16] [c4] [c3]
16	Babita R. Jose (Babita Roslind Jose)	[j13] [j5] [c23] [c17] [c14] [c7]
17	Mohammad Reza Kakoee	[j15] [c29] [c13]
18	Edmund Ming-Kit Lai	[j4]
19	K. Maharatna	[c10]
20	Raveendranatha P. Mahesh (R. Mahesh)	[j4]
21	Dmitri Maslov	[j6] [c19]
22	Seyed Ghassem Miremadi	[c11] [c9] [c8]
23	Vishram Mishra	[j17]
24	Saraju P. Mohanty	[j18] [c44] [c43] [c42] [c41] [j16] [j14] [c38] [c37] [c36] [c35] [c33] [c32] [c30] [c25] [c21] [c20]
25	P. Mythili	[j13] [j5] [c23] [c14] [c7]
26	José L. Núñez-Yáñez (Jose Luis Nunez-Yanez)	[c10]
27	Mahesh Poolakkaparambil	[c43] [c42] [c39] [c38]
28	Dhiraj K. Pradhan	[c45] [j18] [c44] [c41] [c40] [j17] [j16] [j15] [j14] [c39] [c38] [c37] [j12] [j11] [j10] [j8] [c36] [c35] [c34] [c33] [j7] [j6] [c32] [c31] [c30] [j3] [j2] [j1] [c29] [c28] [c27] [c26] [c25] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3]
29	D. Radhakrishnan	[c1]
30	Hafizur Rahaman	[c40] [j12] [j11] [j10] [j9] [j8] [c36] [c33] [j7] [c31] [j3] [j1] [c18] [c17] [c16] [c12] [c6] [c5] [c4]
31	Renji Remesan	[c24] [c23]
32	Rishad Ahmed Shafik (Rishad A. Shafik)	[c45] [c44] [c41]
33	Muhammad A. Shamim	[c24]
34	Biplab K. Sikdar (Biplab Kumar Sikdar)	[c5]
35	Ashutosh Kumar Singh	[j11] [c16]
36	Jawar Singh	[c32] [c30] [c27] [c26] [c25] [c22] [c21] [c20] [c15] [c14]
37	T. Srikanthan	[c1]
38	R. Stapenhurst	[c10]
39	Yi Xin Su	[c22]
40	Luo Sun	[j18]
41	Somsubhra Talapatra	[j9]
42	Anas Abu Taleb	[c34] [c27]
43	A. Prasad Vinod (Achutavarrier Prasad Vinod)	[j4]
44	Pranav Yeolekar	[c44]
45	Hamid R. Zarandi	[c11] [c9] [c8]

Jimson Mathew

Coauthor Index