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Martin Margala
2010 – today
- 2013
[c67]Sai Rahul Chalamalasetti, Kevin T. Lim, Mitch Wright, Alvin AuYoung, Parthasarathy Ranganathan, Martin Margala: An FPGA memcached appliance. FPGA 2013: 245-254- 2012
- [j17]Kemal Kulovic, Martin Margala: Time-Based Embedded Test Instrument with Concurrent Voltage Measurement Capability. J. Electronic Testing 28(5): 653-671 (2012)
- [j16]Samed Maltabas, Kemal Kulovic, Martin Margala: Novel Practical Built-in Current Sensors. J. Electronic Testing 28(5): 673-683 (2012)
- [j15]Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Martin Margala: Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application. Int. J. Reconfig. Comp. 2012 (2012)
- [j14]Sohan Purohit, Martin Margala: Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance. IEEE Trans. VLSI Syst. 20(7): 1327-1331 (2012)
- [c66]Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede, Mitch Wright, Parthasarathy Ranganathan: Evaluating FPGA-acceleration for real-time unstructured search. ISPASS 2012: 200-209
- 2011
- [c65]Osman Kubilay Ekekon, Samed Maltabas, Martin Margala: A multi-GHz PLL Built-In jitter extraction circuit for deep submicron technologies. ECCTD 2011: 657-660
- [c64]Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala: A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks. HPCS 2011: 461-467
- 2010
- [j13]Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, Wim Vanderbauwhede: Radiation-Hardened Reconfigurable Array With Instruction Roll-Back. Embedded Systems Letters 2(4): 123-126 (2010)
- [j12]Sohan Purohit, Marco Lanuzza, Martin Margala: Design Space Exploration of Split-Path Data Driven Dynamic Full Adder. J. Low Power Electronics 6(4): 469-481 (2010)
- [c63]Mohamed El-Hadedy, Martin Margala, Danilo Gligoroski, Svein J. Knapskog: Resource-efficient implementation of Blue Midnight Wish-256 hash function on Xilinx FPGA platform. IAS 2010: 44-47
- [c62]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala: Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths. AHS 2010: 59-65
- [c61]Mohamed El-Hadedy, Sohan Purohit, Martin Margala, Svein J. Knapskog: Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems. AHS 2010: 113-120
- [c60]Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit: A C++-embedded Domain-Specific Language for programming the MORA soft processor array. ASAP 2010: 141-148
- [c59]Samed Maltabas, Osman Kubilay Ekekon, Martin Margala: A new built-in IDDQ testing method using programmable BICS. European Test Symposium 2010: 264
- [c58]Vikas Kaushal, Ignacio Iñiguez-de-la-Torre, Martin Margala: Topology impact on the room temperature performance of THz-range ballistic deflection transistors. ACM Great Lakes Symposium on VLSI 2010: 159-162
- [c57]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala: Design of self correcting radiation hardened digital circuits using decoupled ground bus. ACM Great Lakes Symposium on VLSI 2010: 405-408
- [c56]Sohan Purohit, David Harrington, Martin Margala: An area efficient design methodology for SEU tolerant digital circuits. ISCAS 2010: 981-984
- [c55]Osman Kubilay Ekekon, Samed Maltabas, Martin Margala: Novel programmable built-in current-sensor for analog, digital and mixed-signal circuits. ISCAS 2010: 3545-3548
- [c54]Mohamed El-Hadedy, Martin Margala, Danilo Gligoroski, Svein J. Knapskog: Implementing the Blue Midnight Wish Hash Function on Xilinx Virtex-5 FPGA Platform. ReConFig 2010: 394-399
- [c53]Osman Kubilay Ekekon, Samed Maltabas, Martin Margala, Ugur Çilingiroglu: Power minimization methodology for VCTL topologies. SoCC 2010: 330-333
2000 – 2009
- 2009
- [j11]Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala: Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems. J. Low Power Electronics 5(3): 326-338 (2009)
- [c52]Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, Wim Vanderbauwhede: MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor. AHS 2009: 389-396
- [c51]Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit: Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor. ERSA 2009: 195-201
- [c50]Sai Rahul Chalamalasetti, Wim Vanderbauwhede, Sohan Purohit, Martin Margala: A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model. FPL 2009: 534-538
- [c49]Vikas Kaushal, Quentin Diduck, Martin Margala: Study of leakage current mechanisms in ballistic deflection transistors. ACM Great Lakes Symposium on VLSI 2009: 165-168
- [c48]Samed Maltabas, Martin Margala, Ugur Çilingiroglu: Varicap threshold logic. ACM Great Lakes Symposium on VLSI 2009: 239-244
- [c47]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala: A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic. ACM Great Lakes Symposium on VLSI 2009: 433-436
- [c46]Sohan Purohit, Martin Margala, Marco Lanuzza, Pasquale Corsonello: New performance/power/area efficient, reliable full adder design. ACM Great Lakes Symposium on VLSI 2009: 493-498
- [c45]David Wolpert, Hiroshi Irie, Roman Sobolewski, Paul Ampadu, Quentin Diduck, Martin Margala: Ballistic Deflection Transistors and the Emerging Nanoscale Era. ISCAS 2009: 61-64
- [c44]Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala: Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. VLSI Design 2009: 45-50
- 2008
- [j10]John Liobe, Richard Geisler, Martin Margala: A Novel Application of FM-ADC Toward the Self-Calibration of Phase-Locked Loops. IEEE Trans. on Circuits and Systems 55-I(9): 2491-2504 (2008)
- [c43]
- [c42]Michael Wieckowski, Martin Margala: A portless SRAM Cell using stunted wordline drivers. ISCAS 2008: 584-587
- [c41]Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala: Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. PATMOS 2008: 297-306
- [c40]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello: Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices. ReConFig 2008: 217-222
- [c39]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello: Power/throughput/area efficient PIM-based reconfigurable array for parallel processing. SoCC 2008: 375-378
- 2007
- [j9]Brandon J. Jasionowski, Michelle K. Lay, Martin Margala: A Processor-In-Memory Architecture for Multimedia Compression. IEEE Trans. VLSI Syst. 15(4): 478-483 (2007)
- [c38]Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala: A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. AHS 2007: 119-126
- [c37]John Liobe, Martin Margala: Novel Process and Temperature-Stable BICS for Embedded Analog and Mixed-Signal Test. IOLTS 2007: 231-236
- [c36]Sandeep Patil, Michael Wieckowski, Martin Margala: A Self-Biased Charge-Transfer Sense Amplifier. ISCAS 2007: 3030-3033
- [c35]Richard Geisler, John Liobe, Martin Margala: Process and Temperature Calibration of PLLs with BiST Capabilities. ISCAS 2007: 3864-3867
- 2006
- [j8]Dan Zhao, Shambhu J. Upadhyaya, Martin Margala: Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1411-1418 (2006)
- [c34]
- [c33]Yuxin Wang, Martin Margala: New Embedded Core Testing for System-on-Chips and System-in-Packages. CCECE 2006: 1897-1900
- [c32]Yuxin Wang, D. Makadia, Martin Margala: On-Chip Integrated Antennas - The First Challenge for Reliable on-Chip Wireless Interconnects. CCECE 2006: 2322-2325
- [c31]Pasquale Corsonello, Stefania Perri, Martin Margala: An integrated countermeasure against differential power analysis for secure smart-cards. ISCAS 2006
- [c30]Quentin Diduck, John Liobe, Sadeka Ali, Martin Margala: Process tolerant calibration circuit for PLL applications with BIST. ISCAS 2006
- [c29]Yunan Xiang, R. Pettibon, Martin Margala: A versatile computation module for adaptable multimedia processors. ISCAS 2006
- [c28]Martin Margala: Tutorial: RAM-based Circuits and Architectures for Multimedia and Signal Processing SOCs. SoCC 2006: 321
- 2005
- [j7]Anand Gopalan, Martin Margala, P. R. Mukund: A current based self-test methodology for RF front-end circuits. Microelectronics Journal 36(12): 1091-1102 (2005)
- [j6]Viera Stopjaková, P. Malosek, M. Matej, Vladislav Nagy, Martin Margala: Defect detection in analog and mixed circuits by neural networks using wavelet analysis. IEEE Transactions on Reliability 54(3): 441-448 (2005)
- [j5]Brian Moore, Martin Margala, Christopher J. Backhouse: Design of wireless on-wafer submicron characterization system. IEEE Trans. VLSI Syst. 13(2): 169-180 (2005)
- [c27]Michael Wieckowski, John Liobe, Quentin Diduck, Martin Margala: A New Test Methodology For DNL Error In Flash ADC's. DFT 2005: 582-590
- [c26]Sadeka Ali, Gregory Briggs, Martin Margala: A High Frequency, Low Jitter Auto-Calibration Phase-Locked Loop with Built-in-Self-Test. DFT 2005: 591-600
- [c25]Marco Lanuzza, Stefania Perri, Martin Margala, Pasquale Corsonello: Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. FPL 2005: 13-18
- [c24]Marco Lanuzza, Martin Margala, Pasquale Corsonello: Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. ISLPED 2005: 161-166
- [c23]Michael Wieckowski, Martin Margala: A novel five-transistor (5T) sram cell for high performance cache. SoCC 2005: 101-102
- 2004
- [j4]Viera Stopjaková, P. Malosek, D. Micusík, M. Matej, Martin Margala: Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks. J. Electronic Testing 20(1): 25-37 (2004)
- [j3]Martin Margala, Hongfan Wang: New approach to design for reusability of arithmetic cores in systems-on-chip. Integration 38(2): 185-203 (2004)
- [c22]Quentin Diduck, Martin Margala: 6-bit low power low area frequency modulation based flash ADC. ISCAS (1) 2004: 137-140
- [c21]Sadeka Ali, Martin Margala: A 5.1-GHz CMOS PLL based integer-N frequency synthesizer with ripple-free control voltage and improved acquisition time. ISCAS (4) 2004: 237-240
- [c20]Natalia Kazakova, Martin Margala, Nelson G. Durdle: Sobel edge detection processor for a real-time volume rendering system. ISCAS (2) 2004: 913-916
- [c19]Karthik Sundararaman, Shambhu J. Upadhyaya, Martin Margala: Cost Model Analysis of DFT Based Fault Tolerant SOC Designs. ISQED 2004: 465-469
- [c18]Michael Wieckowski, Martin Margala: A 32Kb SRAM cache using current mode operation and asynchronous wave-pipelined decoders. SoCC 2004: 251-254
- [c17]Antonija Soldo, Anand Gopalan, P. R. Mukund, Martin Margala: A Current Sensor for On-Chip, Non-Intrusive Testing of RF Systems. VLSI Design 2004: 1023-1026
- [c16]Brian Moore, Christopher J. Backhouse, Martin Margala: Design of Wireless Sub-Micron Characterization System. VTS 2004: 341-346
- 2003
- [j2]Marco S. Dragic, Martin Margala: A versatile built-in CMOS sensing device for digital circuit parametric test. IEEE T. Instrumentation and Measurement 52(6): 1756-1764 (2003)
- [c15]Marco S. Dragic, Martin Margala: Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits. DFT 2003: 124-131
- [c14]Dan Zhao, Shambhu J. Upadhyaya, Martin Margala: Control Constrained Resource Partitioning for Complex SoCs. DFT 2003: 425-432
- [c13]Martin Margala, Quentin Diduck, Eric Moule: 1.8V 0.18µm CMOS Novel Successive Approximation ADC. VLSI-SOC 2003: 375-379
- [c12]Martin Margala, John Liobe, Quentin Diduck: Deep-Submicron CMOS Design Methodology for High-Performance Low-Power Analog-to-Digital Converters. VLSI-SOC 2003: 380-385
- [c11]Martin Margala, Magdy A. El-Moursy, Ali El-Moursy, Junmou Zhang, Wendi Beth Heinzelman: 1-V ADPCM Processor for Low-Power Wireless Applications. VLSI-SOC 2003: 386-393
- 2002
- [c10]Viera Stopjaková, D. Micusík, Lubica Benusková, Martin Margala: Neural Networks-Based Parametric Testing of Analog IC. DFT 2002: 408-418
- [c9]Dan Zhao, Shambhu J. Upadhyaya, Martin Margala: Minimizing concurrent test time in SoC's by balancing resource usage. ACM Great Lakes Symposium on VLSI 2002: 77-82
- [c8]Rong Lin, Martin Margala: Novel design and verification of a 16 x 16-b self-repairable reconfigurable inner product processor. ACM Great Lakes Symposium on VLSI 2002: 172-177
- [c7]Srdjan Dragic, Igor M. Filanovsky, Martin Margala: Low-voltage analog current detector supporting at-speed BIST. ISCAS (1) 2002: 593-596
- [c6]Srdjan Dragic, Martin Margala: A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test. ISVLSI 2002: 165-170
- 2001
- [c5]Brian W. Curran, Mary Gifaldi, Jason Martin, Alper Buyuktosunoglu, Martin Margala, David H. Albonesi: Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors. VLSI-SOC 2001: 289-300
- [c4]Natalia Kazakova, R. Sung, Nelson G. Durdle, Martin Margala, Julien Lamoureux: Fast and low-power inner product processor. ISCAS (4) 2001: 646-649
- 2000
- [c3]Martin Margala, Srdjan Dragic, Ahmed El-Abasiry, Samuel Ekpe, Viera Stopjaková: I-V Fast IDDQ Current Sensor for On-Line Mixed-Signal/Analog Test. IOLTW 2000: 92-93
1990 – 1999
- 1999
- [c2]
- [c1]
- 1995
- [j1]Martin Margala, Nelson G. Durdle, Scott Juskiw, V. James Raso, Doug L. Hill: A 33 MHz 16-bit gradient calculator for real-time volume imaging. Computers & Graphics 19(5): 679-684 (1995)
Coauthor Index
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last updated on 2013-03-01 00:41 CET by the dblp team