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Panagiotis Manolios
Pete Manolios
2010 – today
- 2012
[c44]Eugene Goldberg, Panagiotis Manolios: Quantifier elimination by Dependency Sequents. FMCAD 2012: 34-43- [i4]Eugene Goldberg, Panagiotis Manolios: Quantifier Elimination by Dependency Sequents. CoRR abs/1201.5653 (2012)
- [i3]Eugene Goldberg, Panagiotis Manolios: Removal of Quantifiers by Elimination of Boundary Points. CoRR abs/1204.1746 (2012)
- [i2]Eugene Goldberg, Panagiotis Manolios: Checking Satisfiability by Dependency Sequents. CoRR abs/1207.5014 (2012)
- [i1]
- 2011
- [c43]Christine Hang, Panagiotis Manolios, Vasilis Papavasileiou: Synthesizing Cyber-Physical Architectural Models with Real-Time Constraints. CAV 2011: 441-456
- [c42]Panagiotis Manolios, Vasilis Papavasileiou: Pseudo-Boolean Solving by incremental translation to SAT. FMCAD 2011: 41-45
- [c41]Harsh Raju Chamarthi, Panagiotis Manolios: Automated specification analysis using an interactive theorem prover. FMCAD 2011: 46-53
- [c40]Harsh Raju Chamarthi, Peter C. Dillinger, Panagiotis Manolios, Daron Vroon: The ACL2 Sedan Theorem Proving System. TACAS 2011: 291-295
- [c39]Harsh Raju Chamarthi, Peter C. Dillinger, Matt Kaufmann, Panagiotis Manolios: Integrating Testing and Interactive Theorem Proving. ACL2 2011: 4-19
- 2010
- [c38]Eugene Goldberg, Panagiotis Manolios: SAT-Solving Based on Boundary Point Elimination. Haifa Verification Conference 2010: 93-111
- [c37]Panagiotis Manolios, Daron Vroon: Interactive Termination Proofs Using Termination Cores. ITP 2010: 355-370
- [c36]Eugene Goldberg, Panagiotis Manolios: Generating High-Quality Tests for Boolean Circuits by Treating Tests as Proof Encoding. TAP 2010: 101-116
2000 – 2009
- 2009
- [c35]Benjamin Chambers, Panagiotis Manolios, Daron Vroon: Faster SAT solving with better CNF generation. DATE 2009: 1590-1595
- [c34]
- [c33]
- [c32]Matthew Might, Panagiotis Manolios: A PosterioriSoundness for Non-deterministic Abstract Interpretations. VMCAI 2009: 260-274
- 2008
- [j9]David A. Greve, Matt Kaufmann, Panagiotis Manolios, J. Strother Moore, Sandip Ray, José-Luis Ruiz-Reina, Rob Sumners, Daron Vroon, Matthew Wilding: Efficient execution in an automated reasoning environment. J. Funct. Program. 18(1): 15-46 (2008)
- [j8]Panagiotis Manolios, Sudarshan K. Srinivasan: Automatic verification of safety and liveness for pipelined machines using WEB refinement. ACM Trans. Design Autom. Electr. Syst. 13(3) (2008)
- [j7]William G. J. Halfond, Alessandro Orso, Pete Manolios: WASP: Protecting Web Applications Using Positive Tainting and Syntax-Aware Evaluation. IEEE Trans. Software Eng. 34(1): 65-81 (2008)
- [j6]Panagiotis Manolios, Sudarshan K. Srinivasan: A Refinement-Based Compositional Reasoning Framework for Pipelined Machine Verification. IEEE Trans. VLSI Syst. 16(4): 353-364 (2008)
- 2007
- [j5]Peter C. Dillinger, Panagiotis Manolios, Daron Vroon, J. Strother Moore: ACL2s: "The ACL2 Sedan". Electr. Notes Theor. Comput. Sci. 174(2): 3-18 (2007)
- [c31]Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon: BAT: The Bit-Level Analysis Tool. CAV 2007: 303-306
- [c30]Peter C. Dillinger, Panagiotis Manolios, Daron Vroon, J. Strother Moore: ACL2s: "The ACL2 Sedan". ICSE Companion 2007: 59-60
- [c29]Panagiotis Manolios, Daron Vroon, Gayatri Subramanian: Automating component-based system assembly. ISSTA 2007: 61-72
- [c28]
- [c27]Panagiotis Manolios, Marc Galceran Oms, Sergi Oliva Valls: Checking Pedigree Consistency with PCS. TACAS 2007: 339-342
- 2006
- [j4]Panagiotis Manolios, Sudarshan K. Srinivasan: A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures. J. Autom. Reasoning 37(1-2): 93-116 (2006)
- [c26]Panagiotis Manolios, Daron Vroon: Termination Analysis with Calling Context Graphs. CAV 2006: 401-414
- [c25]Roma Kane, Panagiotis Manolios, Sudarshan K. Srinivasan: Monolithic verification of deep pipelines with collapsed flushing. DATE 2006: 1234-1239
- [c24]Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon: Automatic memory reductions for RTL model verification. ICCAD 2006: 786-793
- [c23]Panagiotis Manolios, Daron Vroon: Integrating static analysis and general-purpose theorem proving for termination analysis. ICSE 2006: 873-876
- [c22]Panagiotis Manolios, Yimin Zhang: Implementing Survey Propagation on Graphics Processing Units. SAT 2006: 311-324
- [c21]
- [c20]William G. J. Halfond, Alessandro Orso, Panagiotis Manolios: Using positive tainting and syntax-aware evaluation to counter SQL injection attacks. SIGSOFT FSE 2006: 175-185
- [e1]Panagiotis Manolios, Matthew Wilding (Eds.): Proceedings of the Sixth International Workshop on the ACL2 Theorem Prover and its Applications, ACL2 2006, Seattle, Washington, USA, August 15-16, 2006. ACM 2006, ISBN 0-9788493-0-2
- 2005
- [j3]Panagiotis Manolios, Daron Vroon: Ordinal Arithmetic: Algorithms and Mechanization. J. Autom. Reasoning 34(4): 387-423 (2005)
- [c19]Panagiotis Manolios, Sudarshan K. Srinivasan: A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems. CHARME 2005: 363-366
- [c18]Panagiotis Manolios, Sudarshan K. Srinivasan: Refinement Maps for Efficient Verification of Processor Models. DATE 2005: 1304-1309
- [c17]Panagiotis Manolios, Sudarshan K. Srinivasan: Verification of executable pipelined machines with bit-level interfaces. ICCAD 2005: 855-862
- [c16]Panagiotis Manolios, Sudarshan K. Srinivasan: A complete compositional reasoning framework for the efficient verification of pipelined machines. ICCAD 2005: 863-870
- [c15]Panagiotis Manolios, Sudarshan K. Srinivasan: A computationally ef~cient method based on commitment re~nement maps for verifying pipelined machines. MEMOCODE 2005: 188-197
- [c14]Peter C. Dillinger, Panagiotis Manolios: Enhanced Probabilistic Verification with 3Spin and 3Murphi. SPIN 2005: 272-276
- [c13]
- 2004
- [c12]Panagiotis Manolios, Sudarshan K. Srinivasan: Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements. DATE 2004: 168-175
- [c11]Panagiotis Manolios, Daron Vroon: Integrating Reasoning About Ordinal Arithmetic into ACL2. FMCAD 2004: 82-97
- [c10]Peter C. Dillinger, Panagiotis Manolios: Bloom Filters in Probabilistic Verification. FMCAD 2004: 367-381
- [c9]Peter C. Dillinger, Panagiotis Manolios: Fast and Accurate Bitstate Verification for SPIN. SPIN 2004: 57-75
- 2003
- [j2]Panagiotis Manolios, J. Strother Moore: Partial Functions in ACL2. J. Autom. Reasoning 31(2): 107-127 (2003)
- [c8]
- [c7]
- [c6]Panagiotis Manolios, Richard J. Trefler: A lattice-theoretic characterization of safety and liveness. PODC 2003: 325-333
- [c5]
- 2001
- [j1]Panagiotis Manolios, J. Strother Moore: On the desirability of mechanizing calculational proofs. Inf. Process. Lett. 77(2-4): 173-179 (2001)
- [c4]
- 2000
- [c3]
1990 – 1999
- 1999
- [c2]Panagiotis Manolios, Kedar S. Namjoshi, Robert Summers: Linking Theorem Proving and Model-Checking with Well-Founded Bisimulation. CAV 1999: 369-379
- [c1]Yuan Yu, Panagiotis Manolios, Leslie Lamport: Model Checking TLA+ Specifications. CHARME 1999: 54-66
Coauthor Index
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last updated on 2013-03-16 20:40 CET by the dblp team