Wai-Kei Mak

Cha-Ru Li, Wai-Kei Mak, Ting-Chi Wang: Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement. IEEE Trans. VLSI Syst. 21(3): 523-532 (2013)

Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen: A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules. ASP-DAC 2013: 175-180

Shao-Huan Wang, Yu-Yi Liang, Tien-Yu Kuo, Wai-Kei Mak: ISPD11: Power-Driven Flip-Flop Merging and Relocation. IEEE Trans. on CAD of Integrated Circuits and Systems 31(2): 180-191 (2012)

Yu-Yi Liang, Tien-Yu Kuo, Shao-Huan Wang, Wai-Kei Mak: ALMmap: Technology Mapping for FPGAs With Adaptive Logic Modules. IEEE Trans. on CAD of Integrated Circuits and Systems 31(7): 1134-1139 (2012)

Wai-Kei Mak, Yu-Chen Lin, Chris Chu, Ting-Chi Wang: Pad Assignment for Die-Stacking System-in-Package Design. IEEE Trans. on CAD of Integrated Circuits and Systems 31(11): 1711-1722 (2012)

Wai-Kei Mak, Chris Chu: Rethinking the Wirelength Benefit of 3-D Integration. IEEE Trans. VLSI Syst. 20(12): 2346-2351 (2012)

Gaurav Ajwani, Chris Chu, Wai-Kei Mak: FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 194-204 (2011)

Jackey Z. Yan, Chris C. N. Chu, Wai-Kei Mak: SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement. IEEE Trans. on CAD of Integrated Circuits and Systems 30(7): 1020-1033 (2011)

Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak: Cut-demand based routing resource allocation and consolidation for routability enhancement. ASP-DAC 2011: 533-538

Seong-I. Lei, Wai-Kei Mak: Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign. FPL 2011: 435-440

Shao-Huan Wang, Yu-Yi Liang, Tien-Yu Kuo, Wai-Kei Mak: Power-driven flip-flop merging and relocation. ISPD 2011: 107-114

De-Yu Liu, Wai-Kei Mak, Ting-Chi Wang: Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design. ACM Great Lakes Symposium on VLSI 2010: 423-428

Gaurav Ajwani, Chris Chu, Wai-Kei Mak: FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction. ISPD 2010: 27-34

Jackey Z. Yan, Chris Chu, Wai-Kei Mak: SafeChoice: a novel clustering algorithm for wirelength-driven placement. ISPD 2010: 185-192

Cheng-Yu Wang, Wai-Kei Mak: Signal skew aware floorplanning and bumper signal assignment technique for flip-chip. ASP-DAC 2009: 341-346

Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak: How to consider shorts and guarantee yield rate improvement for redundant wire insertion. ICCAD 2009: 33-38

Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang: Pad assignment for die-stacking System-in-Package design. ICCAD 2009: 249-255

Chun-Yu Chuang, Wai-Kei Mak: Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution. ISQED 2009: 68-73

Wei-Chung Chao, Wai-Kei Mak: Low-power gated and buffered clock network construction. ACM Trans. Design Autom. Electr. Syst. 13(1) (2008)

George A. Constantinides, Wai-Kei Mak, Theerayod Wiangtong: Guest Editorial: Field Programmable Technology. Signal Processing Systems 51(1): 1-2 (2008)

Wai-Kei Mak, Jr-Wei Chen: Voltage Island Generation under Performance Requirement for SoC Designs. ASP-DAC 2007: 798-803

Yi-Ru He, Wai-Kei Mak: Optimal Buffering of FPGA Interconnect for Expected Delay Optimization. FPT 2007: 289-292

Chien-Chang Chen, Wai-Kei Mak: A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers. ASP-DAC 2006: 777-782

George A. Constantinides, Wai-Kei Mak, Phaophak Sirisuk, Theerayod Wiangtong (Eds.): 2006 IEEE International Conference on Field Programmable Technology, FPT 2006, Bangkok, Thailand, December 13-15, 2006. IEEE 2006, isbn 0-7803-9728-2

Wai-Kei Mak: Modern FPGA constrained placement. ASP-DAC 2005: 779-784

Wai-Kei Mak: I/O placement for FPGAs with multiple I/O standards. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 315-321 (2004)

Hao Li, Srinivas Katkoori, Wai-Kei Mak: Power minimization algorithms for LUT-based FPGA technology mapping. ACM Trans. Design Autom. Electr. Syst. 9(1): 33-51 (2004)

Hao Li, Wai-Kei Mak, Srinivas Katkoori: Force-Directed Performance-Driven Placement Algorithm for FPGAs. ISVLSI 2004: 193-198

Wai-Kei Mak, Evangeline F. Y. Young: Temporal logic replication for dynamically reconfigurable FPGA partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 952-959 (2003)

Hao Li, Wai-Kei Mak, Srinivas Katkoori: Efficient LUT-based FPGA technology mapping for power minimization. ASP-DAC 2003: 353-358

Wai-Kei Mak: I/O placement for FPGAs with multiple I/O standards. FPGA 2003: 51-57

Eric S. H. Wong, Evangeline F. Y. Young, Wai-Kei Mak: Clustering based acyclic multi-way partitioning. ACM Great Lakes Symposium on VLSI 2003: 203-206

Wai-Kei Mak: Min-cut partitioning with functional replication fortechnology-mapped circuits using minimum area overhead. IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 491-497 (2002)

Wai-Kei Mak, Evangeline F. Y. Young: Temporal logic replication for dynamically reconfigurable FPGA partitioning. ISPD 2002: 190-195

Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang: Faster and more accurate wiring evaluation in interconnect-centric floorplanning. ACM Great Lakes Symposium on VLSI 2001: 62-67

Wai-Kei Mak: Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead. ISPD 2001: 100-105

Wai-Kei Mak, D. F. Wong: A fast hypergraph min-cut algorithm for circuit partitioning. Integration 30(1): 1-11 (2000)

Wai-Kei Mak, David P. Morton, R. Kevin Wood: Monte Carlo bounding techniques for determining solution quality in stochastic programs. Oper. Res. Lett. 24(1-2): 47-56 (1999)

Wai-Kei Mak, D. F. Wong: A fast hypergraph minimum cut algorithm. ISCAS (6) 1999: 170-173

Wai-Kei Mak, D. F. Wong: Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract). FPGA 1998: 260

Wai-Kei Mak, D. F. Wong: Performance-driven board-level routing for FPGA-based logic emulation. ICCD 1998: 199-201

Wai-Kei Mak, Martin D. F. Wong: On optimal board-level routing for FPGA-based logic emulation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 282-289 (1997)

Wai-Kei Mak, Martin D. F. Wong: Minimum replication min-cut partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1221-1227 (1997)

Wai-Kei Mak, D. F. Wong: Board-level multiterminal net routing for FPGA-based logic emulation. ACM Trans. Design Autom. Electr. Syst. 2(2): 151-167 (1997)

Wai-Kei Mak, D. F. Wong: Channel Segmentation Design for Symmentrical FPGAs. ICCD 1997: 496-501

Wai-Kei Mak, D. F. Wong: Minimum replication min-cut partitioning. ICCAD 1996: 205-210

Wai-Kei Mak, D. F. Wong: On Optimal Board-Level Routing for FPGA-Based Logic Emulation. DAC 1995: 552-556

Wai-Kei Mak, D. F. Wong: Board-level multi-terminal net routing for FPGA-based logic emulation. ICCAD 1995: 339-344

Mee Yee Chan, Francis Y. L. Chin, Chris Chu, Wai-Kei Mak: Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes. SPDP 1993: 285-289

Richard G. Guy, John S. Heidemann, Wai-Kei Mak, Thomas W. Page Jr., Gerald J. Popek, Dieter Rothmeier: Implementation of the Ficus Replicated File System. USENIX Summer 1990: 63-72