Hamid Mahmoodi

Hamid Mahmoodi-Meimand

	2012
j17		Masaoud Houshmand Kaffashian, Reza Lotfi, Khalil Mafinezhad, Hamid Mahmoodi: Impacts of NBTI/PBTI on performance of domino logic circuits with high-k metal-gate devices in nanoscale CMOS. Microelectronics Reliability 52(8): 1655-1659 (2012)
j16		Behrouz Afzal, Behzad Ebrahimi, Ali Afzali-Kusha, Hamid Mahmoodi: Modeling read SNM considering both soft oxide breakdown and negative bias temperature instability. Microelectronics Reliability 52(12): 2948-2954 (2012)
c48		Roberto Menchaca, Hamid Mahmoodi: Impact of transistor aging effects on sense amplifier reliability in nano-scale CMOS. ISQED 2012: 342-346
c47		Hamid Mahmoodi: Reliability enhancement of power gating transistor under time dependent dielectric breakdown. VLSI-SoC 2012: 189-194
c46		Abhishek Guar, Hamid Mahmoodi: Impact of technology scaling on performance of domino logic in nano-scale CMOS. VLSI-SoC 2012: 295-298
	2011
j15		Masaoud Houshmand Kaffashian, Reza Lotfi, Khalil Mafinezhad, Hamid Mahmoodi: Impact of NBTI on performance of domino logic circuits in nano-scale CMOS. Microelectronics Journal 42(12): 1327-1334 (2011)
c45		Farshad Moradi, Georgios Panagopoulos, Georgios Karakonstantis, Dag T. Wisland, Hamid Mahmoodi, Jens Kargaard Madsen, Kaushik Roy: Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology. ICCD 2011: 326-331
c44		Vikram G. Rao, Hamid Mahmoodi: Analysis of reliability of flip-flops under transistor aging effects in nano-scale CMOS technology. ICCD 2011: 439-440
c43		Vish Ganti, Hamid Mahmoodi: Comparative analysis of copper and CNT interconnects for H-tree clock distribution. ICCD 2011: 447-448
c42		Shreyas Kumar Krishnappa, Hamid Mahmoodi: Comparative BTI reliability analysis of SRAM cell designs in nano-scale CMOS technology. ISQED 2011: 384-389
	2010
j14		Minki Cho, Jason Schlessman, Hamid Mahmoodi, Marilyn Wolf, Saibal Mukhopadhyay: Postsilicon Adaptation for Low-Power SRAM under Process Variation. IEEE Design & Test of Computers 27(6): 26-35 (2010)
j13		Somnath Paul, Hamid Mahmoodi, Swarup Bhunia: Low-overhead Fmax calibration at multiple operating points using delay-sensitivity-based path selection. ACM Trans. Design Autom. Electr. Syst. 15(2) (2010)
j12		Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy: Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering. Signal Processing Systems 58(2): 125-137 (2010)
c41		Farshad Moradi, Charles Augustine, Ashish Goel, Georgios Karakonstantis, Tuan Vu Cao, Dag T. Wisland, Hamid Mahmoodi, Kaushik Roy: Data-dependant sense-amplifier flip-flop for low power applications. CICC 2010: 1-4
c40		Anuj Pushkarna, Hamid Mahmoodi: Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS. ACM Great Lakes Symposium on VLSI 2010: 373-376
c39		Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Yngvar Berg, Tuan Vu Cao: New SRAM design using body bias technique for ultra low power applications. ISQED 2010: 468-471
c38		Ankitchandra Shah, Hamid Mahmoodi: Thermal estimation for accurate estimation of impact of BTI aging effects on nano-scale SRAM circuits. SoCC 2010: 230-235
c37		Anuj Pushkarna, Sajna Raghavan, Hamid Mahmoodi: Comparison of performance parameters of SRAM designs in 16nm CMOS and CNTFET technologies. SoCC 2010: 339-342
	2009
j11		Hamid Mahmoodi, Vishy Tirumalashetty, Matthew Cooke, Kaushik Roy: Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating. IEEE Trans. VLSI Syst. 17(1): 33-44 (2009)
c36		Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Snorre Aunet, Tuan Vu Cao, Ali Peiravi: Ultra Low Power Full Adder Topologies. ISCAS 2009: 3158-3161
c35		Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Ali Peiravi, Snorre Aunet, Tuan Vu Cao: New subthreshold concepts in 65nm CMOS technology. ISQED 2009: 162-166
c34		Hamid Mahmoodi, Ali A. Jalali: Virtual Age: Enabling Technologies and Trends. ITNG 2009: 999-1004
c33		Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Tuan Vu Cao: Improved write margin 6T-SRAM for low supply voltage applications. SoCC 2009: 223-226
	2008
j10		Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy: Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique. J. Electronic Testing 24(6): 577-590 (2008)
j9		Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy: Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 174-183 (2008)
c32		Farshad Moradi, Dag T. Wisland, Snorre Aunet, Hamid Mahmoodi, Tuan Vu Cao: 65NM sub-threshold 11T-SRAM for ultra low voltage applications. SoCC 2008: 113-118
	2007
j8		Animesh Datta, Ashish Goel, R. T. Cakici, Hamid Mahmoodi, D. Lekshmanan, Kaushik Roy: Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 1957-1966 (2007)
c31		Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia: Low-overhead design technique for calibration of maximum frequency at multiple operating points. ICCAD 2007: 401-404
c30		Vishwanadh Tirumalashetty, Hamid Mahmoodi: Clock Gating and Negative Edge Triggering for Energy Recovery Clock. ISCAS 2007: 1141-1144
c29		Keejong Kim, Hamid Mahmoodi, Kaushik Roy: A low-power SRAM using bit-line charge-recycling technique. ISLPED 2007: 177-182
c28		Rajani Kuchipudi, Hamid Mahmoodi: Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS. ISQED 2007: 27-32
	2006
j7		Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET. IEEE Trans. VLSI Syst. 14(2): 183-192 (2006)
j6		Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi: Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. IEEE Trans. VLSI Syst. 14(9): 1034-1039 (2006)
c27		Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy: Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. ASP-DAC 2006: 665-670
c26		Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia: Low power synthesis of dynamic logic circuits using fine-grained clock gating. DATE 2006: 862-867
c25		Joyce Yeung, Hamid Mahmoodi: Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS Technologies. SoCC 2006: 261-264
c24		Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici: Double-Gate SOI Devices for Low-Power and High-Performance Applications. VLSI Design 2006: 445-452
	2005
j5		Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1859-1880 (2005)
j4		Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy: A process-tolerant cache architecture for improved yield in nanoscale technologies. IEEE Trans. VLSI Syst. 13(1): 27-38 (2005)
j3		Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy: Low-power scan design using first-level supply gating. IEEE Trans. VLSI Syst. 13(3): 384-395 (2005)
j2		Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy: Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. IEEE Trans. VLSI Syst. 13(11): 1286-1295 (2005)
c23		Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy: Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. Asian Test Symposium 2005: 176-181
c22		Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy: A novel synthesis approach for active leakage power reduction using dynamic supply gating. DAC 2005: 479-484
c21		Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy: A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. DATE 2005: 1136-1141
c20		Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy: Energy recovery clocked dynamic logic. ACM Great Lakes Symposium on VLSI 2005: 468-471
c19		Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peiravi: A high speed and leakage-tolerant domino logic for high fan-in gates. ACM Great Lakes Symposium on VLSI 2005: 478-481
c18		Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici: Double-gate SOI devices for low-power and high-performance applications. ICCAD 2005: 217-224
c17		Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy: Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. ICCD 2005: 206-214
c16		Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy: Process Variation Tolerant Online Current Monitor for Robust Systems. IOLTS 2005: 171-176
c15		Aliakbar Ghadiri, Hamid Mahmoodi-Meimand: Pre-capturing static pulsed flip-flops. ISCAS (3) 2005: 2421-2424
c14		Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy: Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. ISQED 2005: 453-458
c13		Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. ISQED 2005: 490-495
c12		Mesut Meterelliyoz, Hamid Mahmoodi, Kaushik Roy: A leakage control system for thermal stability during burn-in test. ITC 2005: 10
c11		Saibal Mukhopadhyay, Kunhyuk Kang, Hamid Mahmoodi, Kaushik Roy: Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring. ITC 2005: 10
c10		Aliakbar Ghadiri, Hamid Mahmoodi-Meimand: Dual-Edge Triggered Static Pulsed Flip-Flops. VLSI Design 2005: 846-849
c9		Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy: Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. VTS 2005: 292-297
	2004
c8		Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy: First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. DFT 2004: 314-315
c7		Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: Statistical design and optimization of SRAM cell for yield enhancement. ICCAD 2004: 10-13
c6		Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy: A Novel Low-Power Scan Design Technique Using Supply Gating. ICCD 2004: 60-65
c5		Hamid Mahmoodi-Meimand, Kaushik Roy: Dual-edge triggered level converting flip-flops. ISCAS (2) 2004: 661-664
c4		Hamid Mahmoodi-Meimand, Kaushik Roy: Data-retention flip-flops for power-down applications. ISCAS (2) 2004: 677-680
	2003
c3		Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy: Energy recovery clocking scheme and flip-flops for ultra low-energy applications. ISLPED 2003: 54-59
	2002
j1		Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand: Leakage Current in Deep-Submicron CMOS Circuits. Journal of Circuits, Systems, and Computers 11(6): 575-600 (2002)
c2		Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy: High performance and low power FIR filter design based on sharing multiplication. ISLPED 2002: 295-300
	2001
c1		Hamid Mahmoodi-Meimand, Ali Afzali-Kusha: Efficient power clock generation for adiabatic logic. ISCAS (4) 2001: 642-645

Coauthor Index

Colors in the list of coauthors

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