José M. Llabería
List of publications from the DBLP Bibliography Server - FAQ| 2013 | ||
|---|---|---|
| j15 | Jorge Albericio, Pablo Ibáñez, Víctor Viñals, José María Llabería: Exploiting reuse locality on inclusive shared last-level caches. TACO 9(4): 38 (2013) | |
| 2012 | ||
| j14 | Benjamín Sahelices Fernández, Agustín De Dios Hernández, Pablo Ibáñez, Víctor Viñals Yúfera, José María Llabería: Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers. J. Comput. Sci. Technol. 27(1): 75-91 (2012) | |
| j13 | Jorge Albericio, Ruben Gran Tejero, Pablo Ibáñez, Víctor Viñals, José María Llabería: ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache. TACO 8(4): 19 (2012) | |
| 2011 | ||
| j12 | Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería: Filtering directory lookups in CMPs. Microprocessors and Microsystems - Embedded Hardware Design 35(8): 695-707 (2011) | |
| c38 | Ana Bosque, Víctor Viñals, Pablo Ibáñez, José María Llabería: Filtering Directory Lookups in CMPs with Write-Through Caches. Euro-Par (1) 2011: 269-281 | |
| 2010 | ||
| c37 | Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería: Filtering Directory Lookups in CMPs. DSD 2010: 207-216 | |
| 2009 | ||
| j11 | Enrique F. Torres, Pablo Ibáñez, Víctor Viñals Yúfera, José María Llabería: Store Buffer Design for Multibanked Data Caches. IEEE Trans. Computers 58(10): 1307-1320 (2009) | |
| c36 | Benjamín Sahelices Fernández, Pablo Ibáñez, Víctor Viñals, José María Llabería: A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors. Euro-Par 2009: 149-161 | |
| c35 | Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería: On reducing misspeculations in a pipelined scheduler. IPDPS 2009: 1-12 | |
| 2007 | ||
| j10 | Enric Morancho, José María Llabería, Àngel Olivé: A comparison of two policies for issuing instructions speculatively. Journal of Systems Architecture 53(4): 170-183 (2007) | |
| c34 | Enric Morancho, José María Llabería, Àngel Olivé: On reducing energy-consumption by late-inserting instructions into the issue queue. ISLPED 2007: 371-374 | |
| 2006 | ||
| c33 | Agustín De Dios Hernández, Benjamín Sahelices Fernández, Pablo Ibáñez, Víctor Viñals, José M. Llabería: Speeding-Up Synchronizations in DSM Multiprocessors. Euro-Par 2006: 473-484 | |
| c32 | Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería: An Enhancement for a Scheduling Logic Pipelined over two Cycles . ICCD 2006 | |
| 2005 | ||
| j9 | María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas: Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors. TACO 2(3): 247-279 (2005) | |
| c31 | Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería: Store Buffer Design in First-Level Multibanked Data Caches. ISCA 2005: 469-480 | |
| 2004 | ||
| c30 | Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería: Contents Management in First-Level Multibanked Data Caches. Euro-Par 2004: 516-524 | |
| c29 | Enric Morancho, José María Llabería, Àngel Olivé: A Mechanism for Verifying Data Speculation. Euro-Par 2004: 525-534 | |
| 2003 | ||
| j8 | Marta Jiménez, José M. Llabería, Agustin Fernández: A Cost-Effective Implementation of Multilevel Tiling. IEEE Trans. Parallel Distrib. Syst. 14(10): 1006-1020 (2003) | |
| c28 | María Jesús Garzarán, Milos Prvulovic, Víctor Viñals, José María Llabería, Lawrence Rauchwerger, Josep Torrellas: Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation. IEEE PACT 2003: 170-181 | |
| c27 | Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería: Counteracting Bank Misprediction in Sliced First-Level Caches. Euro-Par 2003: 586-596 | |
| c26 | María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas: Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. HPCA 2003: 191-202 | |
| 2002 | ||
| j7 | Marta Jiménez, José M. Llabería, Agustin Fernández: Register tiling in nonrectangular iteration spaces. ACM Trans. Program. Lang. Syst. 24(4): 409-453 (2002) | |
| 2001 | ||
| c25 | Enric Morancho, José María Llabería, Àngel Olivé: Recovery Mechanism for Latency Misprediction. IEEE PACT 2001: 118-128 | |
| 2000 | ||
| c24 | Enric Morancho, José M. Llabería, Àngel Olivé: Two-Level Address Storage and Address Prediction (Research Note). Euro-Par 2000: 960-964 | |
| c23 | Marta Jiménez, José M. Llabería, Agustin Fernández: On the Performance of Hand vs. Automatically Optimized Numerical Codes. HPCA 2000: 183-194 | |
| c22 | Luis M. Ramos, Pablo E. Ibáñez, Víctor Viñals, José M. Llabería: Modeling load address behaviour through recurrences. ISPASS 2000: 101-108 | |
| 1999 | ||
| j6 | A. M. del Corral, José M. Llabería: Minimizing Conflicts Between Vector Streams in Interleaved Memory Systems. IEEE Trans. Computers 48(4): 449-456 (1999) | |
| c21 | Enric Morancho, José M. Llabería, Àngel Olivé: Looking at History to Filter Allocations in Prediction Tables. IEEE PACT 1999: 314-319 | |
| 1998 | ||
| c20 | ||
| c19 | Marta Jiménez, José M. Llabería, Agustin Fernández: Performance Evaluation of Tiling for the Register Level. HPCA 1998: 254-265 | |
| c18 | Marta Jiménez, José M. Llabería, Agustin Fernández, Enric Morancho: A General Algorithm for Tiling the Register Level. International Conference on Supercomputing 1998: 133-140 | |
| c17 | Marta Jiménez, José María Llabería, Agustin Fernández: Loop bounds computation for multilevel tiling. PDP 1998: 445-452 | |
| c16 | A. M. del Corral, José M. Llabería: New Access Order to Reduce Inter-Vector-Conflicts. VECPAR 1998: 425-438 | |
| 1996 | ||
| c15 | A. M. del Corral, José M. Llabería: Increasing the Effective Memory Bandwidth in Multivector Processors. EUROMICRO 1996: 38-45 | |
| c14 | Marta Jiménez, José M. Llabería, Agustin Fernández, Enric Morancho: A Unified Transformation Technique for Multilevel Blocking. Euro-Par, Vol. I 1996: 402-405 | |
| c13 | A. M. del Corral, José M. Llabería: Reducing Inter-Vector-Conflicts in Complex Memory Systems. International Conference on Supercomputing 1996: 382-389 | |
| c12 | A. M. del Corral, José María Llabería: Increasing the Effective Bandwidth of Complex Memory Systems in Multivector Processors. SC 1996: 26 | |
| 1995 | ||
| j5 | Agustin Fernández, José M. Llabería, Miguel Valero-García: Loop Transformation Using Nonunimodular Matrices. IEEE Trans. Parallel Distrib. Syst. 6(8): 832-840 (1995) | |
| c11 | A. M. del Corral, José M. Llabería: Access order to avoid inter-vector-conflicts in complex memory systems. IPPS 1995: 404-410 | |
| 1993 | ||
| j4 | Antonio González, José M. Llabería: Reducing Branch Delay to Zero in Pipelined Processors. IEEE Trans. Computers 42(3): 363-371 (1993) | |
| 1992 | ||
| j3 | Jordi Cortadella, José M. Llabería: Evaluation of A + B = K Conditions Without Carry Propagation. IEEE Trans. Computers 41(11): 1484-1488 (1992) | |
| j2 | Miguel Valero-García, Juan J. Navarro, José María Llabería, Mateo Valero, Tomás Lang: A method for implementation of one-dimensional systolic algorithms with data contraflow using pipelined functional units. VLSI Signal Processing 4(1): 7-25 (1992) | |
| c10 | Mateo Valero, Tomás Lang, José M. Llabería, Montse Peiron, Eduard Ayguadé, Juan J. Navarro: Increasing the Number of Strides for Conflict-Free Vector Access. ISCA 1992: 372-381 | |
| 1991 | ||
| j1 | Mateo Valero, Tomás Lang, José María Llabería, Montse Peiron, Juan J. Navarro, Eduard Ayguadé: Conflict-Free Strides for Vectors in Matched Memories. Parallel Processing Letters 1: 95-102 (1991) | |
| c9 | Agustin Fernández, José M. Llabería, Juan J. Navarro, Miguel Valero-García: Interleaving Partitions of Systolic Algorithms for Programming Distributed Memory Multiprocessors. EDMCC 1991: 90-99 | |
| c8 | Jordi Torres, Eduard Ayguadé, Jesús Labarta, José M. Llabería, Mateo Valero: On Automatic Loop Data-Mapping for Distributed-Memory Multiprocessors. EDMCC 1991: 173-182 | |
| c7 | Jesús Labarta, Eduard Ayguadé, Jordi Torres, Mateo Valero, José M. Llabería: Balanced Loop Partitioning Using GTS. LCPC 1991: 298-312 | |
| 1989 | ||
| c6 | Antonio González, José M. Llabería: Instruction fetch unit for parallel execution of branch instructions. ICS 1989: 417-426 | |
| c5 | Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero: Systematic Hardware Adaptation of Systolic Algorithms. ISCA 1989: 96-104 | |
| 1986 | ||
| c4 | Juan J. Navarro, José M. Llabería, Mateo Valero: Solving Matrix Problems with No Size Restriction on a Systolic Array Processor. ICPP 1986: 676-683 | |
| c3 | Juan J. Navarro, José M. Llabería, Mateo Valero: Computing Size-Independent Matrix Problems on Systolic Array Processors. ISCA 1986: 271-278 | |
| 1985 | ||
| c2 | José M. Llabería, Mateo Valero, Enrique Herrada Lillo, Jesús Labarta: Analysis and Simulation of Multiplexed Single-Bus Networks With and Without Buffering. ISCA 1985: 414-421 | |
| 1983 | ||
| c1 | Mateo Valero, José María Llabería, Jesús Labarta, Emilio Sanvicente, Tomás Lang: A performance evaluation of the multiple bus network for multiprocessor systems. SIGMETRICS 1983: 200-206 | |
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