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Hung-Yi Liu
2010 – today
- 2013
[c8]Hung-Yi Liu, Luca P. Carloni: On learning-based methods for design-space exploration with high-level synthesis. DAC 2013: 50- [c7]Nicola Bombieri, Hung-Yi Liu, Franco Fummi, Luca P. Carloni: A method to abstract RTL IP blocks into C++ code and enable high-level synthesis. DAC 2013: 156
- 2012
- [c6]Hung-Yi Liu, Michele Petracca, Luca P. Carloni: Compositional system-level design exploration with planning of high-level synthesis. DATE 2012: 641-646
- 2011
- [c5]Hung-Yi Liu, Ilias Diakonikolas, Michele Petracca, Luca P. Carloni: Supervised design space exploration by compositional approximation of Pareto sets. DAC 2011: 399-404
2000 – 2009
- 2009
- [j2]Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang: Voltage-Island Partitioning and Floorplanning Under Timing Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 690-702 (2009)
- 2008
- [j1]Chih-Hung Liu, Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Yao-Wen Chang, Sy-Yen Kuo, Shih-Yi Yuan, Yu-Wei Chen: An Efficient Graph-Based Algorithm for ESD Current Path Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1363-1375 (2008)
- 2007
- [c4]Hung-Yi Liu, Wan-Ping Lee, Yao-Wen Chang: A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages. DAC 2007: 887-890
- [c3]Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang: An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning. ICCAD 2007: 650-655
- 2006
- [c2]Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang: Voltage island aware floorplanning for power and timing optimization. ICCAD 2006: 389-394
- [c1]Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Wei-Ting Tu, Chih-Hung Liu, Yao-Wen Chang, Sy-Yen Kuo: Current path analysis for electrostatic discharge protection. ICCAD 2006: 510-515
Coauthor Index
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last updated on 2013-05-29 01:53 CEST by the dblp team