Please note: This is a beta version of the new dblp website.
You can find the classic dblp view of this page here.
You can find the classic dblp view of this page here.
Youn-Long Lin
2010 – today
- 2013
[j32]Shi-Hao Chen, Youn-Long Lin, Mango Chia-Tso Chao: Power-Up Sequence Control for MTCMOS Designs. IEEE Trans. VLSI Syst. 21(3): 413-423 (2013)- 2012
- [j31]Huang-Chih Kuo, Youn-Long Lin: A Hybrid Algorithm for Effective Lossless Compression of Video Display Frames. IEEE Transactions on Multimedia 14(3-1): 500-509 (2012)
- 2011
- [j30]Chia-Ming Hung, Youn-Long Lin: Three-dimensional integrated circuits implementation of multiple applications emphasising manufacture reuse. IET Computers & Digital Techniques 5(3): 179-185 (2011)
- [c48]Huang-Chih Kuo, Youn-Long Lin: A simple and effective lossless compression algorithm for video display frames. ICME 2011: 1-6
- 2010
- [j29]Jian-Wen Chen, Li-Cian Wu, Po-Sheng Liu, Youn-Long Lin: A high-throughput fully hardwired CABAC encoder for QFHD H.264/AVC main profile video. IEEE Trans. Consumer Electronics 56(4): 2529-2536 (2010)
- [j28]Huan-Kai Peng, Youn-Long Lin: An optimal warning-zone-length assignment algorithm for real-time and multiple-QoS on-chip bus arbitration. ACM Trans. Embedded Comput. Syst. 9(4) (2010)
- [j27]Chao-Yang Kao, Cheng-Long Wu, Youn-Long Lin: A High-Performance Three-Engine Architecture for H.264/AVC Fractional Motion Estimation. IEEE Trans. VLSI Syst. 18(4): 662-666 (2010)
- [j26]Chao-Yang Kao, Youn-Long Lin: A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC. IEEE Trans. VLSI Syst. 18(6): 866-874 (2010)
- [c47]
- [c46]
- [c45]Ping Chao, Youn-Long Lin: An elastic software cache with fast prefetching for motion compensation in video decoding. CODES+ISSS 2010: 23-32
2000 – 2009
- 2009
- [j25]Jian-Wen Chen, Youn-Long Lin: A high-performance hardwired CABAC decoder for ultra-high resolution video. IEEE Trans. Consumer Electronics 55(3): 1614-1622 (2009)
- [j24]Yuan-Chun Lin, Youn-Long Lin: A Two-Result-per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder. IEEE Trans. VLSI Syst. 17(6): 838-843 (2009)
- [c44]Huang-Chih Kuo, Jian-Wen Chen, Youn-Long Lin: A high-performance low-power H.264/AVC video decoder accelerator for embedded systems. ESTImedia 2009: 1-8
- [c43]Hui-Ting Yang, Jian-Wen Chen, Huang-Chih Kuo, Youn-Long Lin: An effective dictionary-based display frame compressor. ESTImedia 2009: 28-34
- [c42]Li-Cian Wu, Youn-Long Lin: A High throughput CABAC Encoder for Ultra High Resolution Video. ISCAS 2009: 1048-1051
- 2008
- [c41]Cheng-Long Wu, Chao-Yang Kao, Youn-Long Lin: A high performance three-engine architecture for H.264/AVC fractional motion estimation. ICME 2008: 133-136
- [c40]Chao-Yang Kao, Youn-Long Lin: A high-performance and memory-efficient architecture for H.264/AVC motion estimation. ICME 2008: 141-144
- [c39]Huang-Chih Kuo, Youn-Long Lin: An H.264/AVC full-mode intra-frame encoder for 1080HD video. ICME 2008: 1037-1040
- [c38]
- [c37]Ping Chao, Youn-Long Lin: A motion compensation system with a high efficiency reference frame pre-fetch scheme for QFHD H.264/AVC decoding. ISCAS 2008: 256-259
- 2007
- [i1]Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin: Integration, Verification and Layout of a Complex Multimedia SOC. CoRR abs/0710.4667 (2007)
- 2006
- [c36]Yu-Chien Kao, Huang-Chih Kuo, Yin-Tzu Lin, Chia-Wen Hou, Yi-Hsien Li, Hao-Tin Huang, Youn-Long Lin: A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding. APCCAS 2006: 562-565
- [c35]Shen-Yu Shih, Cheng-Ru Chang, Youn-Long Lin: A near optimal deblocking filter for H.264 advanced video coding. ASP-DAC 2006: 170-175
- [c34]Jian-Wen Chen, Chao-Yang Kao, Youn-Long Lin: Introduction to H.264 advanced video coding. ASP-DAC 2006: 736-741
- [c33]Chao-Yang Kao, Huang-Chih Kuo, Youn-Long Lin: High Performance Fractional Motion Estimation and Mode Decision for H.264/AVC. ICME 2006: 1241-1244
- 2005
- [j23]Kai-Yuan Jan, Chih-Bin Fan, An-Chao Kuo, Wen-Chi Yen, Youn-Long Lin: A platform based SOC design methodology and its application in image compression. IJES 1(1/2): 23-32 (2005)
- [c32]Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin: Integration, Verification and Layout of a Complex Multimedia SOC. DATE 2005: 1116-1117
- [c31]Jian-Wen Chen, Cheng-Ru Chang, Youn-Long Lin: A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC. ISCAS (5) 2005: 4525-4528
- [c30]Sheng-Yu Shih, Cheng-Ru Chang, Youn-Long Lin: An AMBA-compliant deblocking filter IP for H.264/AVC. ISCAS (5) 2005: 4529-4532
- 2004
- [c29]Tien-Wei Hsieh, Youn-Long Lin: A hardware accelerator IP for EBCOT Tier-1 coding in JPEG2000 Standard. ESTImedia 2004: 87-90
- 2002
- [j22]Yih-Chih Chou, Youn-Long Lin: Effective enforcement of path-delay constraints inperformance-driven placement. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 15-22 (2002)
- [c28]Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin: Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium 2002: 356-
- [c27]Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin: Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium 2002: 411-
- 2001
- [c26]Yih-Chih Chou, Youn-Long Lin: A 3-step approach for performance-driven whole-chip routing. ASP-DAC 2001: 187-191
- [c25]Yih-Chih Chou, Youn-Long Lin: A performance-driven standard-cell placer based on a modified force-directed algorithm. ISPD 2001: 24-29
- [c24]Hung-Pin Wen, Chien-Yu Lin, Youn-Long Lin: Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design. ISSS 2001: 233-238
- 2000
- [c23]Michael C.-J. Lin, Youn-Long Lin: A VLSI implementation of the blowfish encryption/decryption algorithm. ASP-DAC 2000: 1-2
- [c22]Tzu-Chieh Tien, Youn-Long Lin: Performance-optimal clustering with retiming for sequential circuits. ASP-DAC 2000: 409-414
- [c21]Hong-Kai Chang, Youn-Long Lin: Array allocation taking into account SDRAM characteristics. ASP-DAC 2000: 497-502
1990 – 1999
- 1999
- [j21]Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin: A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 475-483 (1999)
- [j20]Wei-Kai Cheng, Youn-Long Lin: Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining. ACM Trans. Design Autom. Electr. Syst. 4(3): 231-256 (1999)
- [c20]Yun-Yin Lian, Youn-Long Lin: Layout-based Logic Decomposition for Timing Optimization. ASP-DAC 1999: 229-232
- [c19]Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin: A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. DAC 1999: 262-267
- 1998
- [c18]Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Youn-Long Lin: Integrating logic retiming and register placement. ICCAD 1998: 136-139
- [c17]Yih-Chih Chou, Youn-Long Lin: A graph-partitioning-based approach for multi-layer constrained via minimization. ICCAD 1998: 426-429
- [c16]Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin: Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. ISPD 1998: 12-17
- [c15]Wei-Kai Cheng, Youn-Long Lin: Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture. ISSS 1998: 15-22
- 1997
- [j19]Hsiao-Pin Su, Youn-Long Lin: A phase assignment method for virtual-wire-based hardware emulation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 776-783 (1997)
- [j18]Youn-Long Lin: Recent developments in high-level synthesis. ACM Trans. Design Autom. Electr. Syst. 2(1): 2-21 (1997)
- [c14]
- [c13]Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin: Preserving HDL synthesis hierarchy for cell placement. ISPD 1997: 169-174
- 1996
- [j17]Tsung-Yi Wu, Youn-Long Lin: Register minimization beyond sharing among variables. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1583-1587 (1996)
- 1995
- [j16]Allen C.-H. Wu, Youn-Long Lin: High-Level Synthesis -A Tutorial. IEICE Transactions 78-D(3): 209-218 (1995)
- [j15]Ching-Dong Chen, Yuh-Sheng Lee, Allen C.-H. Wu, Youn-Long Lin: TRACER-fpga: a router for RAM-based FPGA's. IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 371-374 (1995)
- [j14]Yu-Wen Tsay, Youn-Long Lin: A row-based cell placement method that utilizes circuit structural properties. IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 393-397 (1995)
- [j13]Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1076-1084 (1995)
- [c12]Wei-Kai Cheng, Youn-Long Lin: A Transformation-Based Approach for Storage Optimization. DAC 1995: 158-163
- [c11]
- 1994
- [j12]Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin: Performance-driven interconnection optimization for microarchitecture synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 137-149 (1994)
- [j11]Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski: A transformation-based method for loop folding. IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 439-450 (1994)
- [c10]Tsung-Yi Wu, Tzu-Chieh Tien, Allen C.-H. Wu, Youn-Long Lin: A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. EDAC-ETC-EUROASIC 1994: 277-281
- [c9]Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: State Assignment for Power and Area Minimization. ICCD 1994: 250-254
- 1993
- [j10]Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu: An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 12(3): 410-424 (1993)
- [j9]Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin: PLS: a scheduler for pipeline synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 12(9): 1279-1286 (1993)
- [c8]Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: Combining technology mapping and placement for delay-optimization in FPGA designs. ICCAD 1993: 123-127
- 1992
- [j8]Yirng-An Chen, Youn-Long Lin, Long-Wen Chang: A Systolic Algorithm for the k-Nearest Neighbors Problem. IEEE Trans. Computers 41(1): 103-108 (1992)
- [c7]Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin: An effective methodology for functional pipelining. ICCAD 1992: 230-233
- 1991
- [j7]Yu-Chin Hsu, Youn-Long Lin, Hang-Ching Hsieh, Ting-Hai Chao: Combining Logic Minimization and Folding for PLA's. IEEE Trans. Computers 40(6): 706-713 (1991)
- [j6]Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu: LiB: a CMOS cell compiler. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 994-1005 (1991)
- [j5]Min-Siang Lin, Houng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin: Channel density reduction by routing over the cells. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 1067-1071 (1991)
- [c6]Min-Siang Lin, Hourng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin: Channel Density Reduction by Routing Over The Cells. DAC 1991: 120-125
- [c5]Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu: An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. DAC 1991: 481-486
- [c4]Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin: Scheduling for Functional Pipelining and Loop Winding. DAC 1991: 764-769
- 1990
- [j4]Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai: Hybrid routing. IEEE Trans. on CAD of Integrated Circuits and Systems 9(2): 151-157 (1990)
- [j3]Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu: A fast transistor-chaining algorithm for CMOS cell layout. IEEE Trans. on CAD of Integrated Circuits and Systems 9(7): 781-786 (1990)
- [c3]Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin: Optimum and Heuristic Data Path Scheduling Under Resource Constraints. DAC 1990: 65-70
- [c2]Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu: LiB: A Cell Layout Generator. DAC 1990: 474-479
- [c1]Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu: Data Path Allocation Based on Bipartite Weighted Matching. DAC 1990: 499-504
1980 – 1989
- 1989
- [j2]Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai: SILK: a simulated evolution router. IEEE Trans. on CAD of Integrated Circuits and Systems 8(10): 1108-1114 (1989)
- 1988
- [j1]Youn-Long Lin, Daniel D. Gajski: LES: a layout expert system. IEEE Trans. on CAD of Integrated Circuits and Systems 7(8): 868-876 (1988)
Coauthor Index
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2013-05-02 03:33 CEST by the dblp team