Ji-Hoon Lim

Ji-Hoon Lim, Won-Young Jung, Yong-Ju Kim, Inchae Song, Jae-Kyung Wee: A Digitally-Controlled SMPS Using a Novel High-Resolution DPWM Generator Based on a Pseudo Relaxation-Oscillation Technique. IEICE Transactions 96-C(2): 277-284 (2013)

Young San Shin, Jae-Kyung Wee, Jong-Chan Ha, Ji-Hoon Lim, Yong-Ju Kim, Young-Sang Son: A Seamless-Controlled Digital PLL Using Dual Loops for High Speed SoCs. Journal of Circuits, Systems, and Computers 20(4): 741-756 (2011)

Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-Hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seokwon Hwang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun: A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction. J. Solid-State Circuits 46(1): 107-118 (2011)

Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-Hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seokwon Hwang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun: A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction. ISSCC 2010: 434-435

Ji-Hoon Lim, Jong-Chan Ha, Won-Young Jung, Yong-Ju Kim, Jae-Kyung Wee: A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips. IEICE Transactions 90-C(3): 644-648 (2007)