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Semantic ScholarHai Helen Li
Hai (Helen) Li – Hai Li 0001
Person information
- affiliation: Duke University, Department of Electrical and Computer Engineering
- affiliation: University of Pittsburgh, Department of Electrical and Computer Engineering
- affiliation: NYU Polytechnic Institute, Department of Electrical and Computer Engineering
- affiliation: Seagate Technology LLC, Bloomington, USA
- affiliation: Intel Corporation, Santa Clara, USA
- affiliation: Qualcomm Inc., San Diego, USA
- affiliation: Purdue University, Electrical and Computer Engineering
Other persons with the same name
- Hai Li
- Hai Li 0002 — National University of Defense Technology, Changsha, School of Computer
- Hai Li 0003 — University of Lancaster, Department of Computing (and 1 more)
- Hai Li 0004 — Plymouth University, School of Computing and Mathematics
- Hai Li 0005 — Beijing Institute of Technology, School of Information and Electronics
- Hai Li 0006 — Weill Cornell Medicical College, Houston, Methodist Hospital Research Institute (and 2 more)
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2010 – today
- 2017
[j34]Fen Cheng, Yan Yu, Zhongyuan Zhao, Nan Zhao, Yunfei Chen, Hai Li:
Power Allocation for Cache-Aided Small-Cell Networks With Limited Backhaul. IEEE Access 5: 1272-1283 (2017)- [j33]Hai (Helen) Li, Yiran Chen, Chenchen Liu, John Paul Strachan, Noraica Davila:
Looking Ahead for Resistive Memory Technology: A broad perspective on ReRAM technology for future storage and computing. IEEE Consumer Electronics Magazine 6(1): 94-103 (2017) - [j32]Yiran Chen, Hai Helen Li, Ismail Bayram, Enes Eken:
Recent Technology Advances of Emerging Memories. IEEE Design & Test 34(3): 8-22 (2017) - [j31]Enes Eken, Ismail Bayram, Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai (Helen) Li, Yiran Chen:
Giant Spin-Hall assisted STT-RAM and logic design. Integration 58: 253-261 (2017) - [j30]Jie Guo, Wujie Wen, Jingtong Hu, Danghui Wang, Hai Helen Li, Yiran Chen:
FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency. IEEE Trans. on CAD of Integrated Circuits and Systems 36(7): 1167-1180 (2017) - [j29]Miao Hu, Yiran Chen, J. Joshua Yang, Yu Wang, Hai Helen Li:
A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks. IEEE Trans. on CAD of Integrated Circuits and Systems 36(8): 1353-1366 (2017) - [j28]Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Mohammad Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson:
Editorial. IEEE Trans. VLSI Syst. 25(1): 1-20 (2017) - [j27]Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Helen Li:
Cross-Layer Optimization for Multilevel Cell STT-RAM Caches. IEEE Trans. VLSI Syst. 25(6): 1807-1820 (2017) - [c108]Chenchen Liu, Qing Yang, Chi Zhang, Hao Jiang, Qing Wu, Hai Helen Li:
A memristor-based neuromorphic engine with a current sensing scheme for artificial neural network applications. ASP-DAC 2017: 647-652 - [c107]Yandan Wang, Wei Wen, Linghao Song, Hai Helen Li:
Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses. ASP-DAC 2017: 776-781 - [c106]Yandan Wang, Wei Wen, Beiye Liu, Donald M. Chiarulli, Hai (Helen) Li:
Group Scissor: Scaling Neuromorphic Computing Design to Large Neural Networks. DAC 2017: 85:1-85:6 - [c105]Chenchen Liu, Miao Hu, John Paul Strachan, Hai (Helen) Li:
Rescuing Memristor-based Neuromorphic Design with High Defects. DAC 2017: 87:1-87:6 - [c104]Hsin-Pai Cheng, Wei Wen, Chunpeng Wu, Sicheng Li, Hai Helen Li, Yiran Chen:
Understanding the design of IBM neurosynaptic system and its tradeoffs: A user perspective. DATE 2017: 139-144 - [c103]Amr M. Hassan, Chaofei Yang, Chenchen Liu, Hai Helen Li, Yiran Chen:
Hybrid spiking-based multi-layered self-learning neuromorphic system based on memristor crossbar arrays. DATE 2017: 776-781 - [c102]Linghao Song, Xuehai Qian, Hai Li, Yiran Chen:
PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning. HPCA 2017: 541-552 - [c101]Amr M. Hassan, Hai Helen Li, Yiran Chen:
Hardware implementation of echo state networks using memristor double crossbar arrays. IJCNN 2017: 2171-2177 - [i5]Yandan Wang, Wei Wen, Linghao Song, Hai (Helen) Li:
Classification Accuracy Improvement for Neuromorphic Computing Systems with One-level Precision Synapses. CoRR abs/1701.01791 (2017) - [i4]Yandan Wang, Wei Wen, Beiye Liu, Donald M. Chiarulli, Hai Helen Li:
Group Scissor: Scaling Neuromorphic Computing Design to Big Neural Networks. CoRR abs/1702.03443 (2017) - 2016
- [j26]Jianlei Yang, Zhenyu Sun, Xiaobin Wang, Yiran Chen, Hai Li:
Spintronic Memristor as Interface Between DNA and Solid State Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(2): 212-221 (2016) - [j25]Miao Hu, Yandan Wang, Wei Wen, Yu Wang, Hai Li:
Leveraging Stochastic Memristor Devices in Neuromorphic Hardware Systems. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(2): 235-246 (2016) - [j24]Chunpeng Wu, Hsin-Pai Cheng, Sicheng Li, Hai (Helen) Li, Yiran Chen:
ApesNet: a pixel-wise efficient segmentation network for embedded devices. IET Cyper-Phys. Syst.: Theory & Appl. 1(1): 78-85 (2016) - [j23]Shukai Duan, Zhekang Dong, Xiaofang Hu, Lidan Wang, Hai Li:
Small-world Hopfield neural networks with weight salience priority and memristor synapses for digit recognition. Neural Computing and Applications 27(4): 837-844 (2016) - [j22]Zhenyu Sun, Xiuyuan Bi, Wenqing Wu, Sungjoo Yoo, Hai (Helen) Li:
Array Organization and Data Management Exploration in Racetrack Memory. IEEE Trans. Computers 65(4): 1041-1054 (2016) - [j21]Jianlei Yang, Peiyuan Wang, Yaojun Zhang, Yuanqing Cheng, Weisheng Zhao, Yiran Chen, Hai (Helen) Li:
Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach. IEEE Trans. on CAD of Integrated Circuits and Systems 35(3): 380-393 (2016) - [j20]Xiaoxiao Liu, Mengjie Mao, Beiye Liu, Boxun Li, Yu Wang, Hao Jiang, Mark Barnell, Qing Wu, Jianhua Yang, Hai Li, Yiran Chen:
Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators. IEEE Trans. on Circuits and Systems 63(5): 617-628 (2016) - [j19]Hai (Helen) Li, Qinru Qiu, Yu Wang:
Guest Editorial: Design and Applications of Neuromorphic Computing System. IEEE Trans. Multi-Scale Computing Systems 2(4): 223-224 (2016) - [j18]Fubing Mao, Yi-Chung Chen, Wei Zhang, Hai (Helen) Li, Bingsheng He:
Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration. ACM Trans. Design Autom. Electr. Syst. 21(4): 71:1-71:26 (2016) - [j17]Qinru Qiu, Zhe Li, Khadeer Ahmed, Wei Liu, Syed Faisal Habib, Hai (Helen) Li, Miao Hu:
A Neuromorphic Architecture for Context Aware Text Image Recognition. Signal Processing Systems 84(3): 355-369 (2016) - [c100]Xian Zhang, Guangyu Sun, Yaojun Zhang, Yiran Chen, Hai Li, Wujie Wen, Jia Di:
A novel PUF based on cell error rate distribution of STT-RAM. ASP-DAC 2016: 342-347 - [c99]Wei Wen, Chunpeng Wu, Yandan Wang, Kent W. Nixon, Qing Wu, Mark Barnell, Hai Li, Yiran Chen:
A new learning method for inference accuracy, core occupation, and performance co-optimization on TrueNorth chip. DAC 2016: 18:1-18:6 - [c98]Mengjie Mao, Wujie Wen, Xiaoxiao Liu, Jingtong Hu, Danghui Wang, Yiran Chen, Hai Li:
TEMP: thread batch enabled memory partitioning for GPU. DAC 2016: 65:1-65:6 - [c97]Xue Wang, Mengjie Mao, Enes Eken, Wujie Wen, Hai Li, Yiran Chen:
Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache. DATE 2016: 762-767 - [c96]Wujie Wen, Mengjie Mao, Hai Li, Yiran Chen, Yukui Pei, Ning Ge:
A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations. DATE 2016: 1285-1290 - [c95]Chunpeng Wu, Hsin-Pai Cheng, Sicheng Li, Hai Helen Li, Yiran Chen:
ApesNet: A Pixel-wise Efficient Segmentation Network. ESTImedia 2016: 2-8 - [c94]Chaofei Yang, Beiye Liu, Yandan Wang, Yiran Chen, Hai Li, Xian Zhang, Guangyu Sun:
The Applications of NVM Technology in Hardware Security. ACM Great Lakes Symposium on VLSI 2016: 311-316 - [c93]Sicheng Li, Yandan Wang, Wujie Wen, Yu Wang, Yiran Chen, Hai Li:
A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel. ICCAD 2016: 14 - [c92]Chaofei Yang, Beiye Liu, Hai Li, Yiran Chen, Wujie Wen, Mark Barnell, Qing Wu, Jeyavijayan Rajendran:
Security of neuromorphic computing: thwarting learning attacks using memristor's obsolescence effect. ICCAD 2016: 97 - [c91]Chaofei Yang, Chunpeng Wu, Hai Li, Yiran Chen, Mark Barnell, Qing Wu:
Security challenges in smart surveillance systems and the solutions based on emerging nano-devices. ICCAD 2016: 109 - [c90]Chang Song, Beiye Liu, Chenchen Liu, Hai Li, Yiran Chen:
Design techniques of eNVM-enabled neuromorphic computing systems. ICCD 2016: 674-677 - [c89]Sicheng Li, Xiaoxiao Liu, Mengjie Mao, Hai (Helen) Li, Yiran Chen, Boxun Li, Yu Wang:
Heterogeneous systems with reconfigurable neuromorphic computing accelerators. ISCAS 2016: 125-128 - [c88]Somnath Chakraborty, Saumil Joshi, Qiangfei Xia, Hai Li, Yiran Chen, Hao Jiang, Qing Wu, Mark Barnell, J. Joshua Yang:
Built-in selectors self-assembled into memristors. ISCAS 2016: 181-184 - [c87]Beiye Liu, Chaofei Yang, Hai Li, Yiran Chen, Qing Wu, Mark Barnell:
Security of neuromorphic systems: Challenges and solutions. ISCAS 2016: 1326-1329 - [c86]Bonan Yan, Amr Mahmoud Mahmoud, Jianhua Joshua Yang, Qing Wu, Yiran Chen, Hai (Helen) Li:
A neuromorphic ASIC design using one-selector-one-memristor crossbar. ISCAS 2016: 1390-1393 - [c85]Zheng Li, Xiuyuan Bi, Hai (Helen) Li, Yiran Chen, Jianying Qin, Peng Guo, Wenjie Kong, Wenshan Zhan, Xiufeng Han, Hong Zhang, Lingling Wang, Guanping Wu, Hanming Wu:
Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ. ISLPED 2016: 4-9 - [c84]Chenchen Liu, Qing Yang, Bonan Yan, Jianlei Yang, Xiaocong Du, Weijie Zhu, Hao Jiang, Qing Wu, Mark Barnell, Hai Li:
A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy. ISVLSI 2016: 110-115 - [c83]Hsin-Pai Cheng, Wei Wen, Chang Song, Beiye Liu, Hai Li, Yiran Chen:
Exploring the optimal learning technique for IBM TrueNorth platform to overcome quantization loss. NANOARCH 2016: 185-190 - [c82]Wei Wen, Chunpeng Wu, Yandan Wang, Yiran Chen, Hai Li:
Learning Structured Sparsity in Deep Neural Networks. NIPS 2016: 2074-2082 - [c81]Jie Guo, Chuhan Min, Tao Cai, Hai Li, Yiran Chen:
Objnandsim: object-based NAND flash device simulator. NVMSA 2016: 1-6 - [c80]Enes Eken, Ismail Bayram, Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai (Helen) Li, Yiran Chen:
Spin-Hall Assisted STT-RAM Design and Discussion. SLIP 2016: 7:1-7:4 - [i3]Wei Wen, Chunpeng Wu, Yandan Wang, Kent W. Nixon, Qing Wu, Mark Barnell, Hai Li, Yiran Chen:
A New Learning Method for Inference Accuracy, Core Occupation, and Performance Co-optimization on TrueNorth Chip. CoRR abs/1604.00697 (2016) - [i2]Jongsoo Park, Sheng R. Li, Wei Wen, Hai Li, Yiran Chen, Pradeep Dubey:
Holistic SparseCNN: Forging the Trident of Accuracy, Speed, and Size. CoRR abs/1608.01409 (2016) - [i1]Wei Wen, Chunpeng Wu, Yandan Wang, Yiran Chen, Hai Li:
Learning Structured Sparsity in Deep Neural Networks. CoRR abs/1608.03665 (2016) - 2015
- [j16]Yaojun Zhang, Yong Li, Zhenyu Sun, Hai Li, Yiran Chen, Alex K. Jones:
Read Performance: The Newest Barrier in Scaled STT-RAM. IEEE Trans. VLSI Syst. 23(6): 1170-1174 (2015) - [c79]Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Li, Yiran Chen:
An efficient STT-RAM-based register file in GPU architectures. ASP-DAC 2015: 490-495 - [c78]Hai (Helen) Li, Chenchen Liu, Bonan Yan, Chaofei Yang, Linghao Song, Zheng Li, Yiran Chen, Weijie Zhu, Qing Wu, Hao Jiang:
Spiking-based matrix computation by leveraging memristor crossbar array. CISDA 2015: 1-4 - [c77]Chenchen Liu, Bonan Yan, Chaofei Yang, Linghao Song, Zheng Li, Beiye Liu, Yiran Chen, Hai Li, Qing Wu, Hao Jiang:
A spiking neuromorphic design with resistive crossbar. DAC 2015: 14:1-14:6 - [c76]Beiye Liu, Hai Li, Yiran Chen, Xin Li, Qing Wu, Tingwen Huang:
Vortex: variation-aware training for memristor X-bar. DAC 2015: 15:1-15:6 - [c75]Xiaoxiao Liu, Mengjie Mao, Beiye Liu, Hai Li, Yiran Chen, Boxun Li, Yu Wang, Hao Jiang, Mark Barnell, Qing Wu, Jianhua Yang:
RENO: a high-efficient reconfigurable neuromorphic computing accelerator design. DAC 2015: 66:1-66:6 - [c74]Mengjie Mao, Jingtong Hu, Yiran Chen, Hai Li:
VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications. DAC 2015: 83:1-83:6 - [c73]Beiye Liu, Chunpeng Wu, Hai Li, Yiran Chen, Qing Wu, Mark Barnell, Qinru Qiu:
Cloning your mind: security challenges in cognitive system designs and their solutions. DAC 2015: 95:1-95:5 - [c72]Jie Guo, Wujie Wen, Jingtong Hu, Danghui Wang, Hai Li, Yiran Chen:
FlexLevel: a novel NAND flash storage system design for LDPC latency reduction. DAC 2015: 194:1-194:6 - [c71]Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai Li, Yiran Chen:
Giant spin hall effect (GSHE) logic design for low power application. DATE 2015: 1000-1005 - [c70]Yu Wang, Tianqi Tang, Lixue Xia, Boxun Li, Peng Gu, Huazhong Yang, Hai Li, Yuan Xie:
Energy Efficient RRAM Spiking Neural Network for Real Time Classification. ACM Great Lakes Symposium on VLSI 2015: 189-194 - [c69]Yandan Wang, Wei Wen, Hai Li, Miao Hu:
A Novel True Random Number Generator Design Leveraging Emerging Memristor Technology. ACM Great Lakes Symposium on VLSI 2015: 271-276 - [c68]Hai Li, Beiye Liu, Xiaoxiao Liu, Mengjie Mao, Yiran Chen, Qing Wu, Qinru Qiu:
The applications of memristor devices in next-generation cortical processor designs. ISCAS 2015: 17-20 - [c67]Zheng Li, Bonan Yan, Lun Yang, Weisheng Zhao, Yiran Chen, Hai Li:
A new self-reference sensing scheme for TLC MRAM. ISCAS 2015: 593-596 - [c66]Hai (Helen) Li, Xiuyuan Bi, Zhenyu Sun:
The evolutionary spintronic technologies and their usage in high performance computing. SoCC 2015: 350-355 - [c65]Zheng Li, Chenchen Liu, Yandan Wang, Bonan Yan, Chaofei Yang, Jianlei Yang, Hai Li:
An overview on memristor crossabr based neuromorphic circuit and architecture. VLSI-SoC 2015: 52-56 - [e2]
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FacebookAlex K. Jones, Hai (Helen) Li, Ayse Kivilcim Coskun, Martin Margala:
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20 - 22, 2015. ACM 2015, ISBN 978-1-4503-3474-7 [contents]
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20 - 22, 2015. ACM 2015, ISBN 978-1-4503-3474-7 [contents]
[j15]
Miao Hu, Hai Li, Yiran Chen, Qing Wu, Garrett S. Rose, Richard W. Linderman:
Memristor Crossbar-Based Neuromorphic Computing System: A Case Study. IEEE Trans. Neural Netw. Learning Syst. 25(10): 1864-1878 (2014)
Memristor Crossbar-Based Neuromorphic Computing System: A Case Study. IEEE Trans. Neural Netw. Learning Syst. 25(10): 1864-1878 (2014)
[j14]
Zhenyu Sun, Xiuyuan Bi, Hai Li, Weng-Fai Wong, Xiaochun Zhu:
STT-RAM Cache Hierarchy With Multiretention MTJ Designs. IEEE Trans. VLSI Syst. 22(6): 1281-1293 (2014)
STT-RAM Cache Hierarchy With Multiretention MTJ Designs. IEEE Trans. VLSI Syst. 22(6): 1281-1293 (2014)
[c64]
Jianxing Wang, Yenni Tim, Weng-Fai Wong, Zhong-Liang Ong, Zhenyu Sun, Hai Li:
A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores. ASP-DAC 2014: 610-615
A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores. ASP-DAC 2014: 610-615
[c63]
Miao Hu, Yu Wang, Qinru Qiu, Yiran Chen, Hai Li:
The stochastic modeling of TiO2 memristor and its usage in neuromorphic system design. ASP-DAC 2014: 831-836
The stochastic modeling of TiO2 memristor and its usage in neuromorphic system design. ASP-DAC 2014: 831-836
[c62]
Enes Eken, Yaojun Zhang, Wujie Wen, Rajiv V. Joshi, Hai Li, Yiran Chen:
A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability. DAC 2014: 63:1-63:6
A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability. DAC 2014: 63:1-63:6
[c61]
Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen, Hai (Helen) Li:
Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory. DAC 2014: 196:1-196:6
Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory. DAC 2014: 196:1-196:6
[c60]
Boxun Li, Yu Wang, Yiran Chen, Hai (Helen) Li, Huazhong Yang:
ICE: Inline calibration for memristor crossbar-based computing engine. DATE 2014: 1-4
ICE: Inline calibration for memristor crossbar-based computing engine. DATE 2014: 1-4
[c59]
Xiaoxiao Liu, Mengjie Mao, Hai Li, Yiran Chen, Hao Jiang, J. Joshua Yang, Qing Wu, Mark Barnell:
A heterogeneous computing system with memristor-based neuromorphic accelerators. HPEC 2014: 1-6
A heterogeneous computing system with memristor-based neuromorphic accelerators. HPEC 2014: 1-6
[c58]
Beiye Liu, Hai Li, Yiran Chen, Xin Li, Tingwen Huang, Qing Wu, Mark Barnell:
Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems. ICCAD 2014: 63-70
Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems. ICCAD 2014: 63-70
[c57]
Jianxing Wang, Pooja Roy, Weng-Fai Wong, Xiuyuan Bi, Hai Li:
Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration. ICCD 2014: 133-138
Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration. ICCD 2014: 133-138
[c56]
Ling Chen, Chuandong Li, Tingwen Huang, Xing He, Hai Li, Yiran Chen:
STDP learning rule based on memristor with STDP property. IJCNN 2014: 1-6
STDP learning rule based on memristor with STDP property. IJCNN 2014: 1-6
[c55]
Xiaofang Hu, Gang Feng, Hai Li, Yiran Chen, Shukai Duan:
An adjustable memristor model and its application in small-world neural networks. IJCNN 2014: 7-14
An adjustable memristor model and its application in small-world neural networks. IJCNN 2014: 7-14
[c54]
Qing Wu, Beiye Liu, Yiran Chen, Hai Li, Qiuwen Chen, Qinru Qiu:
Bio-inspired computing with resistive memories - models, architectures and applications. ISCAS 2014: 834-837
Bio-inspired computing with resistive memories - models, architectures and applications. ISCAS 2014: 834-837
[c53]
Hai Li, Miao Hu, Chuandong Li, Shukai Duan:
Memristor Modeling - Static, Statistical, and Stochastic Methodologies. ISVLSI 2014: 406-411
Memristor Modeling - Static, Statistical, and Stochastic Methodologies. ISVLSI 2014: 406-411
[c52]
Qinru Qiu, Zhe Li, Khadeer Ahmed, Hai (Helen) Li, Miao Hu:
Neuromorphic acceleration for context aware text image recognition. SiPS 2014: 268-273
Neuromorphic acceleration for context aware text image recognition. SiPS 2014: 268-273
[c51]
Hai Li, Miao Hu, Xiaoxiao Liu, Mengjie Mao, Chuandong Li, Shukai Duan:
Emerging memristor technology enabled next generation cortical processor. SoCC 2014: 377-382
Emerging memristor technology enabled next generation cortical processor. SoCC 2014: 377-382
[e1]
Joseph R. Cavallaro, Tong Zhang, Alex K. Jones, Hai (Helen) Li:
Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21 - 23, 2014. ACM 2014, ISBN 978-1-4503-2816-6 [contents]
Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21 - 23, 2014. ACM 2014, ISBN 978-1-4503-2816-6 [contents]
[j13]
Yiran Chen, Weng-Fai Wong, Hai Li, Cheng-Kok Koh, Yaojun Zhang, Wujie Wen:
On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations. JETC 9(2): 16:1-16:22 (2013)
On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations. JETC 9(2): 16:1-16:22 (2013)
[j12]
Yong Li, Yaojun Zhang, Hai Li, Yiran Chen, Alex K. Jones:
C1C: A configurable, compiler-guided STT-RAM L1 cache. TACO 10(4): 52:1-52:22 (2013)
C1C: A configurable, compiler-guided STT-RAM L1 cache. TACO 10(4): 52:1-52:22 (2013)
[j11]
Bo Zhao, Jun Yang, Youtao Zhang, Yiran Chen, Hai Li:
Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices. ACM Trans. Design Autom. Electr. Syst. 18(4): 57:1-57:18 (2013)
Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices. ACM Trans. Design Autom. Electr. Syst. 18(4): 57:1-57:18 (2013)
[c50]
Miao Hu, Hai Li, Yiran Chen, Qing Wu, Garrett S. Rose:
BSB training scheme implementation on memristor-based circuit. CISDA 2013: 80-87
BSB training scheme implementation on memristor-based circuit. CISDA 2013: 80-87
[c49]
Beiye Liu, Miao Hu, Hai Li, Yiran Chen, Chun Xue:
Bio-inspired ultra lower-power neuromorphic computing engine for embedded systems. CODES+ISSS 2013: 23:1
Bio-inspired ultra lower-power neuromorphic computing engine for embedded systems. CODES+ISSS 2013: 23:1
[c48]
Beiye Liu, Miao Hu, Hai Li, Zhi-Hong Mao, Yiran Chen, Tingwen Huang, Wei Zhang:
Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine. DAC 2013: 7:1-7:6
Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine. DAC 2013: 7:1-7:6
[c47]
Zhenyu Sun, Wenqing Wu, Hai (Helen) Li:
Cross-layer racetrack memory design for ultra high density and low power consumption. DAC 2013: 53:1-53:6
Cross-layer racetrack memory design for ultra high density and low power consumption. DAC 2013: 53:1-53:6
[c46]
Jie Guo, Wujie Wen, Yaojun Zhang, Sicheng Li, Hai Li, Yiran Chen:
DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems. DATE 2013: 380-385
DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems. DATE 2013: 380-385
[c45]
Xiuyuan Bi, Mohamed Anis Weldon, Hai Li:
STT-RAM designs supporting dual-port accesses. DATE 2013: 853-858
STT-RAM designs supporting dual-port accesses. DATE 2013: 853-858
[c44]
Yi-Chung Chen, Wei Zhang, Hai (Helen) Li:
A hardware security scheme for RRAM-based FPGA. FPL 2013: 1-4
A hardware security scheme for RRAM-based FPGA. FPL 2013: 1-4
[c43]
Mengjie Mao, Hai (Helen) Li, Alex K. Jones, Yiran Chen:
Coordinating prefetching and STT-RAM based last-level cache management for multicore systems. ACM Great Lakes Symposium on VLSI 2013: 55-60
Coordinating prefetching and STT-RAM based last-level cache management for multicore systems. ACM Great Lakes Symposium on VLSI 2013: 55-60
[c42]
Yaojun Zhang, Ismail Bayram, Yu Wang, Hai Li, Yiran Chen:
ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications. ICCAD 2013: 9-16
ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications. ICCAD 2013: 9-16
[c41]
Qiuwen Chen, Qinru Qiu, Hai Li, Qing Wu:
A neuromorphic architecture for anomaly detection in autonomous large-area traffic monitoring. ICCAD 2013: 202-205
A neuromorphic architecture for anomaly detection in autonomous large-area traffic monitoring. ICCAD 2013: 202-205
[c40]
Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Li:
Unleashing the potential of MLC STT-RAM caches. ICCAD 2013: 429-436
Unleashing the potential of MLC STT-RAM caches. ICCAD 2013: 429-436
[c39]
Feng Ji, Hai (Helen) Li, Bryant T. Wysocki, Clare Thiem, Nathan R. McDonald:
Memristor-based synapse design and a case study in reconfigurable systems. IJCNN 2013: 1-6
Memristor-based synapse design and a case study in reconfigurable systems. IJCNN 2013: 1-6
[c38]
Jianxing Wang, Yenni Tim, Weng-Fai Wong, Hai (Helen) Li:
A practical low-power memristor-based analog neural branch predictor. ISLPED 2013: 175-180
A practical low-power memristor-based analog neural branch predictor. ISLPED 2013: 175-180
[c37]
Zhijie Chen, Lu Zhang, Xiuyuan Bi, Hai Li:
A pseudo-weighted sensing scheme for memristor based cross-point memory. NANOARCH 2013: 38-39
A pseudo-weighted sensing scheme for memristor based cross-point memory. NANOARCH 2013: 38-39
[j10]
Zhenyu Sun, Xiang Chen, Yaojun Zhang, Hai Li, Yiran Chen:
Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder. JETC 8(2): 13:1-13:16 (2012)
Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder. JETC 8(2): 13:1-13:16 (2012)
[j9]
Yiran Chen, Hai Li, Xiaobin Wang, Wenzhong Zhu, Wei Xu, Tong Zhang:
A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme. J. Solid-State Circuits 47(2): 560-573 (2012)
A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme. J. Solid-State Circuits 47(2): 560-573 (2012)
[j8]
Zhenyu Sun, Hai Li, Yiran Chen, Xiaobin Wang:
Voltage Driven Nondestructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory. IEEE Trans. VLSI Syst. 20(11): 2020-2030 (2012)
Voltage Driven Nondestructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory. IEEE Trans. VLSI Syst. 20(11): 2020-2030 (2012)
[c36]
Xiang Chen, Jian Zheng, Yiran Chen, Wei Zhang, Hai Li:
Fine-grained dynamic voltage scaling on OLED display. ASP-DAC 2012: 807-812
Fine-grained dynamic voltage scaling on OLED display. ASP-DAC 2012: 807-812
[c35]
Miao Hu, Hai Li, Qing Wu, Garrett S. Rose:
Hardware realization of BSB recall function using memristor crossbar arrays. DAC 2012: 498-503
Hardware realization of BSB recall function using memristor crossbar arrays. DAC 2012: 498-503
[c34]
Robinson E. Pino, Hai (Helen) Li, Yiran Chen, Miao Hu, Beiye Liu:
Statistical memristor modeling and case study in neuromorphic computing. DAC 2012: 585-590
Statistical memristor modeling and case study in neuromorphic computing. DAC 2012: 585-590
[c33]
Xiuyuan Bi, Chao Zhang, Hai Li, Yiran Chen, Robinson E. Pino:
Spintronic memristor based temperature sensor design with CMOS current reference. DATE 2012: 1301-1306
Spintronic memristor based temperature sensor design with CMOS current reference. DATE 2012: 1301-1306
[c32]
Bo Zhao, Jun Yang, Youtao Zhang, Yiran Chen, Hai Li:
Architecting a common-source-line array for bipolar non-volatile memory devices. DATE 2012: 1451-1454
Architecting a common-source-line array for bipolar non-volatile memory devices. DATE 2012: 1451-1454
[c31]
Xiuyuan Bi, Zhenyu Sun, Hai Li, Wenqing Wu:
Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches. ICCAD 2012: 88-94
Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches. ICCAD 2012: 88-94
[c30]
Miao Hu, Hai Li, Qing Wu, Garrett S. Rose, Yiran Chen:
Memristor crossbar based hardware realization of BSB recall function. IJCNN 2012: 1-7
Memristor crossbar based hardware realization of BSB recall function. IJCNN 2012: 1-7
[c29]
Hui Wang, Hai Li, Robinson E. Pino:
Memristor-based synapse design and training scheme for neuromorphic computing architecture. IJCNN 2012: 1-5
Memristor-based synapse design and training scheme for neuromorphic computing architecture. IJCNN 2012: 1-5
[c28]
Zhenyu Sun, Hai Li, Wenqing Wu:
A dual-mode architecture for fast-switching STT-RAM. ISLPED 2012: 45-50
A dual-mode architecture for fast-switching STT-RAM. ISLPED 2012: 45-50
[c27]
Zhenyu Sun, Xiuyuan Bi, Hai Li:
Process variation aware data management for STT-RAM cache design. ISLPED 2012: 179-184
Process variation aware data management for STT-RAM cache design. ISLPED 2012: 179-184
[c26]
Xiuyuan Bi, Hai Li, Jae-Joon Kim:
Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design. ISVLSI 2012: 374-379
Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design. ISVLSI 2012: 374-379
[c25]