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Miriam Leeser
2010 – today
- 2013
[c57]Peter Grossmann, Miriam Leeser, Marvin Onabajo: Minimum energy operation for clustered island-style FPGAs. FPGA 2013: 157-166- [c56]Nicholas Moore, Miriam Leeser, Laurie A. Smith King: Kernel Specialization for Improved Adaptability and Performance on Graphics Processing Units (GPUs). IPDPS 2013: 1037-1048
- 2012
- [j29]Nicholas Moore, Miriam Leeser, Laurie A. Smith King: VForce: An environment for portable applications on high performance systems with accelerators. J. Parallel Distrib. Comput. 72(9): 1144-1156 (2012)
- [j28]Peter Grossmann, Miriam Leeser, Marvin Onabajo: Minimum Energy Analysis and Experimental Verification of a Latch-Based Subthreshold FPGA. IEEE Trans. on Circuits and Systems 59-II(12): 942-946 (2012)
- [c55]George Eichinger, Kaushik Chowdhury, Miriam Leeser: Cognitive Radio Universal Software Hardware. FCCM 2012: 240
- [c54]Mary Ellen Tie, Miriam Leeser: Implementing Murf: Accelerating Large State Space Exploration on FPGAs. FCCM 2012: 243
- [c53]Scott Bailie, Miriam Leeser: Incremental clustering applied to radar deinterleaving: a parameterized FPGA implementation. FPGA 2012: 25-28
- [c52]George Eichinger, Kaushik Chowdhury, Miriam Leeser: CRUSH: Cognitive Radio Universal Software Hardware. FPL 2012: 26-32
- [c51]Saoni Mukherjeet, Nicholas Moore, James Brock, Miriam Leeser: CUDA and OpenCL implementations of 3D CT reconstruction for biomedical imaging. HPEC 2012: 1-6
- 2011
- [j27]Miriam Leeser, Devon Yablonski, Dana Brooks, Laurie A. Smith King: The challenges of writing portable, correct and high performance libraries for GPUs. SIGARCH Computer Architecture News 39(4): 2-7 (2011)
- [c50]Jainik Kathiara, Miriam Leeser: An Autonomous Vector/Scalar Floating Point Coprocessor for FPGAs. FCCM 2011: 33-36
- [c49]Peter Grossmann, Miriam Leeser: A prototype FPGA for subthreshold-optimized CMOS (abstract only). FPGA 2011: 279
- 2010
- [j26]Xiaojun Wang, Miriam Leeser: VFloat: A Variable Precision Fixed- and Floating-Point Library for Reconfigurable Hardware. TRETS 3(3): 16 (2010)
- [c48]Nicholas Moore, Miriam Leeser, Laurie A. Smith King: Efficient template matching with variable size templates in CUDA. SASP 2010: 77-80
- [e3]David R. Kaeli, Miriam Leeser (Eds.): Proceedings of 3rd Workshop on General Purpose Processing on Graphics Processing Units, GPGPU 2010, Pittsburgh, Pennsylvania, USA, March 14, 2010. ACM International Conference Proceeding Series 425, ACM 2010, ISBN 978-1-60558-935-0
2000 – 2009
- 2009
- [j25]Ben Cordes, Miriam Leeser: Parallel Backprojection: A Case Study in High-Performance Reconfigurable Computing. EURASIP J. Emb. Sys. 2009 (2009)
- [j24]Vinay Sriram, Miriam Leeser: FPGA Supercomputing Platforms, Architectures, and Techniques for Accelerating Computationally Complex Algorithms. EURASIP J. Emb. Sys. 2009 (2009)
- [j23]Xiaojun Wang, Miriam Leeser: A truly two-dimensional systolic array FPGA implementation of QR decomposition. ACM Trans. Embedded Comput. Syst. 9(1) (2009)
- [c47]Abderrahmane Bennis, Miriam Leeser, Gilead Tadmor: Implementing a Highly Parameterized Digital PIV System on Reconfigurable Hardware. ASAP 2009: 32-37
- [c46]Perhaad Mistry, Sherman Braganza, David R. Kaeli, Miriam Leeser: Accelerating phase unwrapping and affine transformations for optical quadrature microscopy using CUDA. GPGPU 2009: 28-37
- [c45]Abderrahmane Bennis, Miriam Leeser, Gilead Tadmor: The Effect of Parameterization on a Reconfigurable Implementation of PIV. ERSA 2009: 105-111
- [e2]David R. Kaeli, Miriam Leeser (Eds.): Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units, GPGPU 2009, Washington, DC, USA, March 8, 2009. ACM International Conference Proceeding Series 383, ACM 2009, ISBN 978-1-60558-517-8
- 2008
- [j22]David R. Kaeli, Miriam Leeser: Special issue: General-purpose processing using graphics processing units. J. Parallel Distrib. Comput. 68(10): 1305-1306 (2008)
- [j21]David R. Kaeli, Miriam Leeser: Acknowledgment to special issue reviewers. J. Parallel Distrib. Comput. 68(10): 1402 (2008)
- [j20]Joshua Noseworthy, Miriam Leeser: Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA. IEEE Trans. VLSI Syst. 16(8): 1083-1090 (2008)
- [c44]Sherman Braganza, Miriam Leeser: An efficient implementation of a phase unwrapping kernel on reconfigurable hardware. ASAP 2008: 138-143
- [c43]Mary Ellen Fuess, Miriam Leeser, Tim Leonard: An FPGA Implementation of Explicit-State Model Checking. FCCM 2008: 119-126
- [c42]Sherman Braganza, Miriam Leeser: An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable Hardware. FCCM 2008: 316-317
- [c41]Xiaojun Wang, Miriam Leeser: Efficient FPGA implementation of qr decomposition using a systolic array architecture. FPGA 2008: 260
- 2007
- [j19]Nicholas Moore, Albert Conti, Miriam Leeser, Laurie A. Smith King: Vforce: An Extensible Framework for Reconfigurable Supercomputing. IEEE Computer 40(3): 39-49 (2007)
- [j18]Heather Quinn, Miriam Leeser, Laurie A. Smith King: Dynamo: a runtime partitioning system for FPGA-based HW/SW image processing systems. J. Real-Time Image Processing 2(4): 179-190 (2007)
- [c40]Sherman Braganza, Miriam Leeser: The 1D Discrete Cosine Transform For Large Point Sizes Implemented On Reconfigurable Hardware. ASAP 2007: 101-106
- [c39]Xiaojun Wang, Miriam Leeser: K-means Clustering for Multispectral Images Using Floating-Point Divide. FCCM 2007: 151-162
- [c38]Nicholas Moore, Albert Conti, Miriam Leeser, Laurie A. Smith King: Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable Hardware. FCCM 2007: 229-238
- 2006
- [j17]Miriam Leeser, Scott Hauck, Russell Tessier: Field-Programmable Gate Arrays in Embedded Systems. EURASIP J. Emb. Sys. 2006 (2006)
- [j16]Peter Soderquist, Miriam Leeser, Juan Carlos Rojas: Enabling MPEG-2 video playback in embedded systems through improved data cache efficiency. IEEE Transactions on Multimedia 8(1): 81-89 (2006)
- [c37]Joshua Noseworthy, Miriam Leeser: Efficient Use of Communications Between an FPGAs Embedded Processor and its Reconfigurable Logic. ERSA 2006: 191-197
- [c36]Haiqian Yu, Miriam Leeser: Automatic Sliding Window Operation Optimization for FPGA-Based. FCCM 2006: 76-88
- [c35]Xiaojun Wang, Sherman Braganza, Miriam Leeser: Advanced Components in the Variable Precision Floating-Point Library. FCCM 2006: 249-258
- [c34]Joshua Noseworthy, Miriam Leeser: Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic. FPGA 2006: 233
- [c33]Ben Cordes, Miriam Leeser, Eric L. Miller, Richard W. Linderman: Poster reception - Improving the performance of parallel backprojection on a reconfigurable supercomputer. SC 2006: 149
- 2005
- [j15]Miriam Leeser, Srdjan Coric, Eric L. Miller, Haiqian Yu, Marc Trepanier: Parallel-Beam Backprojection: An FPGA Implementation Optimized for Medical Imaging. VLSI Signal Processing 39(3): 295-311 (2005)
- [c32]Ben Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel: Enabling a RealTime Solution for Neuron Detection with Reconfigurable Hardware (abstract only). FPGA 2005: 264
- [c31]Ben Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel: Enabling a Real-Time Solution for Neuron Detection with Reconfigurable Hardware. IEEE International Workshop on Rapid System Prototyping 2005: 128-134
- 2004
- [c30]Laurie A. Smith King, Miriam Leeser, Heather Quinn: Dynamo: A Runtime Partitioning System. ERSA 2004: 145-154
- [c29]Miriam Leeser, Shawn Miller, Haiqian Yu: Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications. FCCM 2004: 147-155
- [c28]Wang Chen, Panos Kosmas, Miriam Leeser, Carey M. Rappaport: An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm. FPGA 2004: 213-222
- 2003
- [c27]Heather Quinn, Laurie A. Smith King, Miriam Leeser, Waleed Meleis: Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines. FCCM 2003: 173-
- [c26]Juan Carlos Rojas, Miriam Leeser: Programming portable optimized multimedia applications. ACM Multimedia 2003: 291-294
- 2002
- [c25]Srdjan Coric, Miriam Leeser, Eric L. Miller, Marc Trepanier: Parallel-beam backprojection: an FPGA implementation optimized for medical imaging. FPGA 2002: 217-226
- [c24]Pavle Belanovic, Miriam Leeser: A Library of Parameterized Floating-Point Modules and Their Use. FPL 2002: 657-666
- 2001
- [j14]Silviu M. S. A. Chiricescu, Miriam Leeser, Mankuan Michael Vai: Design and analysis of a dynamically reconfigurable three-dimensional FPGA. IEEE Trans. VLSI Syst. 9(1): 186-196 (2001)
- [c23]Mike Estlick, Miriam Leeser, James Theiler, John J. Szymanski: Algorithmic transformations in the implementation of K- means clustering on reconfigurable hardware. FPGA 2001: 103-110
- [c22]Laurie A. Smith King, Heather Quinn, Miriam Leeser, Demetris G. Galatopoullos, Elias S. Manolakos: Run-Time Execution of Reconfigurable Hardware in a Java Environment. ICCD 2001: 380-387
- 2000
- [j13]Shantanu Tarafdar, Miriam Leeser: A data-centric approach to high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1251-1267 (2000)
- [j12]Yanbing Li, Miriam Leeser: HML, a novel hardware description language and its translation to VHDL. IEEE Trans. VLSI Syst. 8(1): 1-8 (2000)
- [c21]Ali M. Shankiti, Miriam Leeser: Implementing a RAKE receiver for wireless communications on an FPGA-based computer system. FPGA 2000: 145-151
1990 – 1999
- 1998
- [j11]Miriam Leeser, Waleed Meleis, Mankuan Michael Vai, Silviu M. S. A. Chiricescu, Weidong Xu, Paul M. Zavracky: Rothko: A Three-Dimensional FPGA. IEEE Design & Test of Computers 15(1): 16-23 (1998)
- [c20]Shantanu Tarafdar, Miriam Leeser: The DT-Model: High-Level Synthesis Using Data Transfers. DAC 1998: 114-117
- [c19]Goran Doncev, Miriam Leeser, Shantanu Tarafdar: High Level Synthesis for Designing Custom Computing Hardware. FCCM 1998: 326-328
- [c18]Shantanu Tarafdar, Miriam Leeser, Zixin Yin: Integrating floorplanning in data-transfer based high-level synthesis. ICCAD 1998: 412-417
- [c17]Goran Doncev, Miriam Leeser, Shantanu Tarafdar: Truly Rapid Prototyping Requires High-Level Synthesis. International Workshop on Rapid System Prototyping 1998: 101-
- 1997
- [c16]Waleed Meleis, Miriam Leeser, Paul M. Zavracky, Mankuan Michael Vai: Architectural Design of a Three Dimensional FPGA. ARVLSI 1997: 256-269
- [c15]Miriam Leeser, Waleed Meleis, Mankuan Michael Vai, Paul M. Zavracky: Rothko: A three dimensional FPGA architecture, its fabrication, and design tools. FPL 1997: 21-30
- [c14]Peter Soderquist, Miriam Leeser: Memory Traffic and Data Cache Behavior of an MPEG-2 Software Decoder. ICCD 1997: 417-422
- [c13]Peter Soderquist, Miriam Leeser: Optimizing the Data Cache Performance of a Software MPEG-2 Video Decoder. ACM Multimedia 1997: 291-301
- 1996
- [j10]Peter Soderquist, Miriam Leeser: Area and Performance Tradeoffs in Floating-Point Divide and Square-Root Implementations. ACM Comput. Surv. 28(3): 518-564 (1996)
- 1995
- [j9]Andrés Takach, Wayne Wolf, Miriam Leeser: An Automaton Model for Scheduling Constraints in Synchronous Machines. IEEE Trans. Computers 44(1): 1-12 (1995)
- [j8]Mark Aagaard, Miriam Leeser: Verifying a Logic-Synthesis Algorithm and Implementation: A Case Study in Software Verification. IEEE Trans. Software Eng. 21(10): 822-833 (1995)
- [c12]Peter Soderquist, Miriam Leeser: An Area/Performance Comparison of Subtractive and Multiplicative Divide/Square Root Implementations. IEEE Symposium on Computer Arithmetic 1995: 132-139
- [c11]Miriam Leeser, John W. O'Leary: Verification of a subtractive radix-2 square root algorithm and implementation. ICCD 1995: 526-531
- 1994
- [j7]Mark Aagaard, Miriam Leeser: A Methodology for Efficient Hardware Verification. Formal Methods in System Design 5(1/2): 95-117 (1994)
- [j6]Mark Aagaard, Miriam Leeser: PBS: proven Boolean simplification. IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 459-470 (1994)
- [c10]Mark H. Linderman, Miriam Leeser: Simulation of digital circuits in the presence of uncertainty. ICCAD 1994: 248-251
- [c9]
- [c8]John W. O'Leary, Miriam Leeser, Jason Hickey, Mark Aagaard: Non-Restoring Integer Square Root: A Case Study in Design by Principled Optimization. TPCD 1994: 52-71
- 1993
- [j5]Miriam Leeser, Richard Chapman, Mark Aagaard, Mark H. Linderman, Stephan Meier: High level synthesis and generating FPGAs with the BEDROC system. VLSI Signal Processing 6(2): 191-214 (1993)
- [j4]Miriam Leeser: High level synthesis and generation FPGAs with the BEDROC system. VLSI Signal Processing 6(3): 7 (1993)
- [c7]John W. O'Leary, Mark H. Linderman, Miriam Leeser, Mark Aagaard: HML: A Hardware Description Language Based on Standard ML. CHDL 1993: 327-334
- [c6]
- [c5]Mark Aagaard, Miriam Leeser, Phillip J. Windley: Toward a Super Duper Hardware Tactic. HUG 1993: 399-412
- 1992
- [c4]Mark Aagaard, Miriam Leeser: Verifying a Logic Synthesis Tool in Nuprl: A Case Study in Software Verification. CAV 1992: 69-81
- [c3]
- 1991
- [j3]David A. Basin, Geoffrey M. Brown, Miriam Leeser: Formally verified synthesis of combinational CMOS circuits. Integration 11(3): 235-250 (1991)
- [c2]
- 1990
- [e1]Miriam Leeser, Geoffrey Brown (Eds.): Hardware Specification, Verification and Synthesis: Mathematical Aspects, Mathematical Science Institute Workshop, Cornall University, Ithaca, New York, USA, July 5-7, 1989, Proceedings. Lecture Notes in Computer Science 408, Springer 1990, ISBN 3-540-97226-9
1980 – 1989
- 1989
- [j2]Miriam Leeser: Reasoning about the function and timing of integrated circuits with interval temporal logic. IEEE Trans. on CAD of Integrated Circuits and Systems 8(12): 1233-1246 (1989)
- [c1]Geoffrey M. Brown, Miriam Leeser: From Programs to Transistors: Verifying Hardware Synthesis Tools. Hardware Specification, Verification and Synthesis 1989: 129-151
- 1986
- [j1]William F. Clocksin, Miriam Leeser: Automatic determination of signal flow through MOS transistor networks. Integration 4(1): 53-63 (1986)
Coauthor Index
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last updated on 2013-10-02 11:08 CEST by the dblp team