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 | 2009 | |
|---|---|---|
| j24 |      | Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash. J. Electronic Testing 25(2-3): 127-144 (2009) |
| j23 | | Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Is triple modular redundancy suitable for yield improvement? IET Computers & Digital Techniques 3(6): 581-592 (2009) |
| c55 | | Christian Landrault: Something I Always Wanted to Know About Test, But Was Afraid to Ask. European Test Symposium 2009 |
| 2008 | ||
| j22 | | Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault: A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. J. Electronic Testing 24(4): 353-364 (2008) |
| c54 | | Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Improving Diagnosis Resolution without Physical Information. DELTA 2008: 210-215 |
| c53 | | Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Using TMR Architectures for Yield Improvement. DFT 2008: 7-15 |
| c52 | | Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Yield Improvement, Fault-Tolerance to the Rescue?. IOLTS 2008: 165-166 |
| c51 | | Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: SoC Yield Improvement: Redundant Architectures to the Rescue? ITC 2008: 1 |
| 2007 | ||
| j21 | | Christian Landrault, Erik Jan Marinissen: Editorial. IET Computers & Digital Techniques 1(3): 145 (2007) |
| c50 | | Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Slow write driver faults in 65nm SRAM technology: analysis and March test solution. DATE 2007: 528-533 |
| c49 |  | Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: A Mixed Approach for Unified Logic Diagnosis. DDECS 2007: 239-242 |
| c48 | | Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: DERRIC: A Tool for Unified Logic Diagnosis. European Test Symposium 2007: 13-20 |
| c47 | | Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. European Test Symposium 2007: 77-84 |
| c46 | | Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. European Test Symposium 2007: 97-104 |
| c45 | | Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga: A concurrent approach for testing address decoder faults in eFlash memories. ITC 2007: 1-10 |
| c44 | | Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. VTS 2007: 47-52 |
| c43 | | Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. VTS 2007: 361-368 |
| 2006 | ||
| j20 | | Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electronic Testing 22(1): 89-99 (2006) |
| c42 | | Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich: Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. VLSI-SoC 2006: 403-408 |
| c41 | | Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: An Overview of Failure Mechanisms in Embedded Flash Memories. VTS 2006: 108-113 |
| 2005 | ||
| c40 | | Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault: Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. PATMOS 2005: 540-549 |
| c39 | | Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault: Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. VLSI-SoC 2005: 267-281 |
| 2004 | ||
| j19 | | Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: Power-Driven Routing-Constrained Scan Chain Design. J. Electronic Testing 20(6): 647-660 (2004) |
| c38 | | Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Design of Routing-Constrained Low Power Scan Chains. DATE 2004: 62-67 |
| c37 | | Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Design of Routing-Constrained Low Power Scan Chains. DELTA 2004: 287-294 |
| 2003 | ||
| j18 | | Marie-Lise Flottes, Christian Landrault, A. Petitqueux: A Unified DFT Approach for BIST and External Test. J. Electronic Testing 19(1): 49-60 (2003) |
| j17 | | Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault: A Ring Architecture Strategy for BIST Test Pattern Generation. J. Electronic Testing 19(3): 223-231 (2003) |
| j16 | | |
| c36 | | Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC 2003: 488-493 |
| 2002 | ||
| j15 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich: High Defect Coverage with Low-Power Test Sequences in a BIST Environment. IEEE Design & Test of Computers 19(5): 44-52 (2002) |
| j14 | | |
| j13 | | René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Hardware Generation of Random Single Input Change Test Sequences. J. Electronic Testing 18(2): 145-157 (2002) |
| c35 | | Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Test Power: a Big Issue in Large SOC Designs. DELTA 2002: 447-449 |
| c34 | | Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Power Driven Chaining of Flip-Flops in Scan Architectures. ITC 2002: 796-803 |
| c33 | | René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: On Using Efficient Test Sequences for BIST. VTS 2002: 145-152 |
| 2001 | ||
| j12 | | Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. J. Electronic Testing 17(3-4): 233-241 (2001) |
| c32 | | Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. Asian Test Symposium 2001: 253-258 |
| c31 | | David Bernard, Christian Landrault, Pascal Nouet: Interconnect Capacitance Modelling in a VDSM CMOS Technology. VLSI-SOC 2001: 133-144 |
| c30 | | René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Random Adjacent Sequences: An Efficient Solution for Logic BIST. VLSI-SOC 2001: 413-424 |
| c29 | | Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: A Gated Clock Scheme for Low Power Scan-Based BIST. IOLTW 2001: 87-89 |
| c28 | | Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich: A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. VTS 2001: 306-311 |
| 2000 | ||
| j11 | | |
| j10 | | Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Paulo J. Teixeira, Marcelino B. Santos: Low Power BIST by Filtering Non-Detecting Vectors. J. Electronic Testing 16(3): 193-202 (2000) |
| c27 | | Marie-Lise Flottes, Christian Landrault, A. Petitqueux: Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. Asian Test Symposium 2000: 404- |
| c26 | | Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: An adjacency-based test pattern generator for low power BIST design. Asian Test Symposium 2000: 459-464 |
| c25 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. IOLTW 2000: 121-126 |
| c24 | | Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch: Low power BIST design by hypergraph partitioning: methodology and architectures. ITC 2000: 652-661 |
| c23 | | Laurent Bréhélin, Olivier Gascuel, Gilles Caraux, Patrick Girard, Christian Landrault: Hidden Markov and Independence Models with Patterns for Sequential BIST. VTS 2000: 359-368 |
| 1999 | ||
| j9 | | |
| j8 | | Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel: A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. J. Electronic Testing 14(1-2): 95-102 (1999) |
| c22 | | Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. Asian Test Symposium 1999: 89-94 |
| c21 | | A. Toulouse, David Bernard, Christian Landrault, Pascal Nouet: Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts. DATE 1999: 576-580 |
| c20 | | Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. Great Lakes Symposium on VLSI 1999: 24- |
| c19 | | Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, Paulo J. Teixeira, Marcelino B. Santos: Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) 1999: 110-113 |
| c18 | | Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: A Test Vector Inhibiting Technique for Low Energy BIST Design. VTS 1999: 407-412 |
| 1998 | ||
| c17 | | Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault: A Ring Architecture Strategy for BIST Test Pattern Generation. Asian Test Symposium 1998: 418-423 |
| c16 | | Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel: A BIST Structure to Test Delay Faults in a Scan Environment. Asian Test Symposium 1998: 435-439 |
| 1997 | ||
| j7 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac: A non-iterative gate resizing algorithm for high reduction in power consumption. Integration 24(1): 37-52 (1997) |
| c15 | | Marc Perbost, Ludovic Le Lan, Christian Landrault: Automatic Testability Analysis of Boards and MCMs at Chip Level. Asian Test Symposium 1997: 36-41 |
| c14 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac: A gate resizing technique for high reduction in power consumption. ISLPED 1997: 281-286 |
| c13 | | Christophe Fagot, Patrick Girard, Christian Landrault: On Using Machine Learning for Logic BIST. ITC 1997: 338-346 |
| c12 | | Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch: An optimized BIST test pattern generator for delay testing. VTS 1997: 94-100 |
| c11 | | J. Abraham, P. Frankl, Christian Landrault, Meryem Marzouki, Paolo Prinetto, Chantal Robach, Pascale Thévenod-Fosse: Hardware Test: Can We Learn from Software Testing? VTS 1997: 320-321 |
| 1996 | ||
| c10 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez: A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. ITC 1996: 286-293 |
| c9 | | S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: A new test pattern generation method for delay fault testing. VTS 1996: 296-301 |
| 1995 | ||
| j6 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch: An advanced diagnostic method for delay faults in combinational faulty circuits. J. Electronic Testing 6(3): 277-294 (1995) |
| j5 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez: Delay fault diagnosis in sequential circuits based on path tracing. Integration 19(3): 199-218 (1995) |
| c8 | | S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault: Test configurations to enhance the testability of sequential circuits. Asian Test Symposium 1995: 160-168 |
| c7 | | Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre: Is High-Level Test Synthesis Just Design for Test? ITC 1995: 294 |
| c6 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez: Diagnostic of path and gate delay faults in non-scan sequential circuits. VTS 1995: 380-386 |
| 1994 | ||
| c5 | | D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. EDAC-ETC-EUROASIC 1994: 518-523 |
| 1993 | ||
| c4 | | D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. ITC 1993: 705-713 |
| 1992 | ||
| j4 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Delay-Fault Diagnosis by Critical-Path Tracing. IEEE Design & Test of Computers 9(4): 27-32 (1992) |
| c3 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch: A Novel Approach to Delay-Fault Diagnosis. DAC 1992: 357-360 |
| 1991 | ||
| j3 | | Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch: Fault modeling and fault equivalence in CMOS technology. J. Electronic Testing 2(3): 229-241 (1991) |
| 1990 | ||
| c2 | | Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch: Fault modelling and fault equivalence in CMOS technology. EURO-DAC 1990: 407-412 |
| 1980 | ||
| j2 | | Yves Crouzet, Christian Landrault: Design of Self-Checking MOS-LSI Circuits: Application to a Four-Bit Microprocessor. IEEE Trans. Computers 29(6): 532-537 (1980) |
| 1978 | ||
| j1 | | Alain Costes, Christian Landrault, Jean-Claude Laprie: Reliability and Availability Models for Maintained Systems Featuring Hardware Failures and Design Faults. IEEE Trans. Computers 27(6): 548-560 (1978) |
| c1 | | Christian Landrault, Jean-Claude Laprie: SURF - A Program for Modeling and Reliability Prediction for Fault-Tolerant Computing Systems. Jerusalem Conference on Information Technology 1978: 17-26 |
Colors in the list of coauthors
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