Shashi Kumar

Mohammad Danish, Shashi Kumar, Surendra Kumar: A note on the solution of singular boundary value problems arising in engineering and applied sciences: Use of OHAM. Computers & Chemical Engineering 36: 57-67 (2012)

Maurizio Palesi, Shashi Kumar, Radu Marculescu: Network-on-chip architectures and design methodologies. Microprocessors and Microsystems - Embedded Hardware Design 35(2): 83-84 (2011)

Rickard Holsmark, Shashi Kumar: An Abstraction to Support Design of Deadlock-free Routing Algorithms for Large and Hierarchical NoCs. CIT 2011: 59-66

Maurizio Palesi, Shashi Kumar, Vincenzo Catania: Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks-on-Chip. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 426-440 (2010)

Maurizio Palesi, Rickard Holsmark, Xiaohang Wang, Shashi Kumar, Mei Yang, Yingtao Jiang, Vincenzo Catania: An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip. DSD 2010: 37-44

Saad Mubeen, Shashi Kumar: Designing Efficient Source Routing for Mesh Topology Network on Chip Platforms. DSD 2010: 181-188

Rickard Holsmark, Shashi Kumar, Maurizio Palesi: A Multi-level Routing Scheme and Router Architecture to Support Hierarchical Routing in Large Network on Chip Platforms. Euro-Par Workshops 2010: 153-161

Maurizio Palesi, Shashi Kumar, Vincenzo Catania: Bandwidth-aware routing algorithms for networks-on-chip platforms. IET Computers & Digital Techniques 3(5): 413-429 (2009)

Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania: Application Specific Routing Algorithms for Networks on Chip. IEEE Trans. Parallel Distrib. Syst. 20(3): 316-330 (2009)

Andres Mejia, Maurizio Palesi, Jose Flich, Shashi Kumar, Pedro López, Rickard Holsmark, José Duato: Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs. IEEE Trans. VLSI Syst. 17(3): 356-369 (2009)

Rafael Tornero, Shashi Kumar, Saad Mubeen, Juan Manuel Orduña: Distance Constrained Mapping to Support NoC Platforms Based on Source Routing. Euro-Par Workshops 2009: 16-25

Shelly Bansal, Daya Gupta, V. K. Panchal, Shashi Kumar: Swarm Intelligence Inspired Classifiers in Comparison with Fuzzy and Rough Classifiers: A Remote Sensing Approach. IC3 2009: 284-294

Rickard Holsmark, Shashi Kumar, Maurizio Palesi, Andres Mejia: HiRA: A methodology for deadlock free routing in hierarchical networks on chip. NOCS 2009: 2-11

Sonal Kumar, Daya Gupta, V. K. Panchal, Shashi Kumar: Enabling web services for Classification of Satellite Image. SWWS 2009: 89-94

Tomas Bengtsson, Shashi Kumar, Raimund Ubar, Artur Jutman, Zebo Peng: Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols. IET Computers & Digital Techniques 2(6): 445-460 (2008)

Rickard Holsmark, Maurizio Palesi, Shashi Kumar: Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions. Journal of Systems Architecture - Embedded Systems Design 54(3-4): 427-440 (2008)

Dario Frazzetta, Giuseppe Dimartino, Maurizio Palesi, Shashi Kumar, Vincenzo Catania: Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. DSD 2008: 18-25

Maurizio Palesi, Giuseppe Longo, Salvatore Signorino, Rickard Holsmark, Shashi Kumar, Vincenzo Catania: Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms. NOCS 2008: 97-106

Mohammad Danish, Arees Qamareen, Shashi Kumar, Surendra Kumar: Letter to the Editor. Computers & Chemical Engineering 31(10): 1364-1365 (2007)

Shashi Kumar, Sanjeev Kumar, Prakash, Ravi Shankar, M. K. Tiwari, Shashi Bhushan Kumar: Prediction of flow stress for carbon steels using recurrent self-organizing neuro fuzzy networks. Expert Syst. Appl. 32(3): 777-788 (2007)

Rickard Holsmark, Shashi Kumar: Corrections to Chen and Chiu's Fault Tolerant Routing Algorithm for Mesh Networks. J. Inf. Sci. Eng. 23(6): 1649-1662 (2007)

Davide Bertozzi, Shashi Kumar, Maurizio Palesi: Networks-on-Chip: Emerging Research Topics and Novel Ideas. VLSI Design 2007 (2007)

Maurizio Palesi, Shashi Kumar, Rickard Holsmark, Vincenzo Catania: Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms. IPDPS 2007: 1-8

Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania: A methodology for design of application specific deadlock-free routing algorithms for NoC systems. CODES+ISSS 2006: 142-147

Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng: Off-Line Testing of Delay Faults in NoC Interconnects. DSD 2006: 677-680

Rickard Holsmark, Maurizio Palesi, Shashi Kumar: Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. DSD 2006: 696-703

Maurizio Palesi, Shashi Kumar, Rickard Holsmark: A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures. SAMOS 2006: 373-384

Daniel Andreasson, Shashi Kumar: Slack-time aware routing in NoC systems. ISCAS (3) 2005: 2353-2356

Mikael Millberg, Erland Nilsson, Rikard Thid, Shashi Kumar, Axel Jantsch: The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip. VLSI Design 2004: 693-696

Sushil Chandra Jain, Anshul Kumar, Shashi Kumar: Hybrid Multi-FPGA Board Evaluation by Permitting Limited Multi-Hop Routing. Design Autom. for Emb. Sys. 8(4): 309-326 (2003)

Tang Lei, Shashi Kumar: A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture. DSD 2003: 180-189

Tang Lei, Shashi Kumar: Algorithms and Tools for Network on Chip Based System Design. SBCCI 2003: 163-168

Rickard Holsmark, Magnus Högberg, Shashi Kumar: Modelling and Evaluation of a Network on Chip Architecture Using SDL. SDL Forum 2003: 166-182

Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar: Extending Platform-Based Design to Network on Chip Systems. VLSI Design 2003: 401-

Sushil Chandra Jain, Anshul Kumar, Shashi Kumar: Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards. FPT 2002: 298-301

Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani: A Network on Chip Architecture and Design Methodology. ISVLSI 2002: 117-124

Sushil Chandra Jain, Anshul Kumar, Shashi Kumar: Hybrid Multi-FPGA Board Evaluation by Limiting Multi-Hop Routing. IEEE International Workshop on Rapid System Prototyping 2002: 66-

Axel Jantsch, Shashi Kumar, Ahmed Hemani: A Metamodel for Studying Concepts in Electronic System Design. IEEE Design & Test of Computers 17(3): 78-85 (2000)

Sushil Chandra Jain, Anshul Kumar, Shashi Kumar: Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards. FPL 2000: 201-210

Aviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar, M. Balakrishnan: Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming. VLSI Design 2000: 110-113

Sushil Chandra Jain, Shashi Kumar, Anshul Kumar: Evaluation of Various Routing Architectures for Multi-FPGA Boards. VLSI Design 2000: 262-267

Ahmed Hemani, Thomas Meincke, Shashi Kumar, Adam Postula, Thomas Olsson, Peter Nilsson, Johnny Öberg, Peeter Ellervee, Dan Lundqvist: Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style. DAC 1999: 873-878

Axel Jantsch, Shashi Kumar, Ahmed Hemani: The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems. DATE 1999: 256-262

Thomas Meincke, Ahmed Hemani, Shashi Kumar, Peeter Ellervee, Johnny Öberg, Thomas Olsson, Peter Nilsson, Dan Lindqvist, Hannu Tenhunen: Globally asynchronous locally synchronous architecture for large high-performance ASICs. ISCAS (2) 1999: 512-515

Bengt Svantesson, Shashi Kumar, Ahmed Hemani: A Methodology and Algorithms for Efficient Interprocess Communication Synthesis from System Description in SDL. VLSI Design 1998: 78-84

Sitanshu Jain, M. Balakrishnan, Anshul Kumar, Shashi Kumar: Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library. VLSI Design 1998: 400-405

Gaurav Aggarwal, Nitin Thaper, Kamal Aggarwal, M. Balakrishnan, Shashi Kumar: A Novel Reconfigurable Co-Processor Architecture. VLSI Design 1997: 370-375

S. Harikumar, Shashi Kumar: Iterative Deepening Multiobjective A. Inf. Process. Lett. 58(1): 11-15 (1996)

B. M. Subraya, Anshul Kumar, Shashi Kumar: An HOL based framework for design of correct high level synthesizers. VLSI Design 1995: 249-254

C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer: High Level Design Experiences with IDEAS. VLSI Design 1993: 110