| 2010 | ||
|---|---|---|
| j5 | Jieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea I. Ismail: SACTA: A Self-Adjusting Clock Tree Architecture for Adapting to Thermal-Induced Delay Variation. IEEE Trans. VLSI Syst. 18(9): 1323-1336 (2010) | |
| 2008 | ||
| j4 | Ja Chun Ku, Yehea I. Ismail: Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 241-248 (2008) | |
| 2007 | ||
| j3 | Ja Chun Ku, Yehea I. Ismail: On the Scaling of Temperature-Dependent Effects. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1882-1888 (2007) | |
| j2 | Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail: Thermal Management of On-Chip Caches Through Power Density Minimization. IEEE Trans. VLSI Syst. 15(5): 592-604 (2007) | |
| j1 | Ja Chun Ku, Yehea I. Ismail: Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits. IEEE Trans. VLSI Syst. 15(8): 963-970 (2007) | |
| c8 | Jieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea I. Ismail: A self-adjusting clock tree architecture to cope with temperature variations. ICCAD 2007: 75-82 | |
| c7 | ||
| c6 | Ja Chun Ku, Yehea I. Ismail: A Compact and Accurate Temperature-Dependent Model for CMOS Circuit Delay. ISCAS 2007: 3736-3739 | |
| c5 | Ja Chun Ku, Yehea I. Ismail: Thermal-aware methodology for repeater insertion in low-power VLSI circuits. ISLPED 2007: 86-91 | |
| c4 | Serkan Ozdemir, Arindam Mallik, Ja Chun Ku, Gokhan Memik, Yehea I. Ismail: Variable latency caches for nanoscale processor. SC 2007: 20 | |
| 2006 | ||
| c3 | Ja Chun Ku, Yehea I. Ismail: Area optimization for leakage reduction and thermal stability in nanometer scale technologies. ASP-DAC 2006: 231-236 | |
| c2 | Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail: Power density minimization for highly-associative caches in embedded processors. ACM Great Lakes Symposium on VLSI 2006: 100-104 | |
| 2005 | ||
| c1 | Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail: Thermal Management of On-Chip Caches Through Power Density Minimization. MICRO 2005: 283-293 | |
| 1 | Yehea I. Ismail | |
| 2 | Jieyi Long | |
| 3 | Arindam Mallik | |
| 4 | Gokhan Memik | |
| 5 | Seda Ogrenci Memik (Seda Ogrenci) | |
| 6 | Serkan Ozdemir |
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