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 | 2013 | |
|---|---|---|
| c73 |      | Hanno Eichelberger, Patrick Heckeler, Stefan Huster, Sebastian Burg, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel, Bastian Schlich: Beschleunigte Robustheitstests für verhaltensbeschreibende Zustandsmaschinen. MBMV 2013: 161-170 |
| c72 | | Stefan Huster, Patrick Heckeler, Jürgen Ruf, Sebastian Burg, Thomas Kropf, Wolfgang Rosenstiel: A Software Testing Framework to Integrate Formal Verification Results. MBMV 2013: 183-192 |
| c71 |  | Patrick Heckeler, Bastian Schlich, Thomas Kropf: Accelerated robustness testing of state-based components using reverse execution. SAC 2013: 1188-1195 |
| 2012 | ||
| c70 | | Alexander Grünhage, Jörg Behrend, Patrick Heckeler, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel, Djones Lettnin: Optimized Static Parameter Assignment for Semiformal Software Verification. MBMV 2012: 25-35 |
| 2011 | ||
| j9 | | Patrick Heckeler, Jörg Behrend, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel, Roland Weiss: DWARF-driven Equivalence Checking of UML Statecharts and Software Components. Softwaretechnik-Trends 31(3) (2011) |
| c69 | | Jörg Behrend, Djones Lettnin, Patrick Heckeler, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel: Scalable hybrid verification for embedded software. DATE 2011: 179-184 |
| c68 | | Jörg Behrend, Patrick Heckeler, Stefan Huster, Djones Lettnin, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel: Scalable and Extendable Hybrid Verification Platform. MBMV 2011: 259-268 |
| 2010 | ||
| c67 | | Stefan Lämmermann, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel, Alexander Viehl, Alexander Jesser, Lars Hedrich: Towards assertion-based verification of heterogeneous system designs. DATE 2010: 1171-1176 |
| c66 | | Patrick Heckeler, Jörg Behrend, Thomas Kropf, Jürgen Ruf, Wolfgang Rosenstiel, Roland J. Weiss: State-based Analysis and UML-driven Equivalence Checking for C++ State Machines. FM+AM 2010: 49-62 |
| c65 | | Florian Merz, Carsten Sinz, Hendrik Post, Thomas Gorges, Thomas Kropf: Abstract Testing: Connecting Source Code Verification with Requirements. QUATIC 2010: 89-96 |
| 2009 | ||
| c64 | | Djones Lettnin, Pradeep Kumar Nalla, Jörg Behrend, Jürgen Ruf, Joachim Gerlach, Thomas Kropf, Wolfgang Rosenstiel, Volker Schönknecht, Stephan Reitemeyer: Semiformal verification of temporal properties in automotive hardware dependent software. DATE 2009: 1214-1217 |
| c63 | | Hendrik Post, Carsten Sinz, Florian Merz, Thomas Gorges, Thomas Kropf: Linking Functional Requirements and Software Verification. RE 2009: 295-302 |
| 2008 | ||
| j8 | | Alexander Jesser, Stefan Lämmermann, Alexander Pacholik, Roland Weiss, Jürgen Ruf, Lars Hedrich, Wolfgang Fengler, Thomas Kropf, Wolfgang Rosenstiel: Advanced Assertion-Based Design for Mixed-Signal Verification. IEICE Transactions 91-A(12): 3548-3555 (2008) |
| c62 | | Djones Lettnin, Pradeep Kumar Nalla, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel, Tobias Kirsten, Volker Schönknecht, Stephan Reitemeyer: Verification of Temporal Properties in Automotive Embedded Software. DATE 2008: 164-169 |
| 2007 | ||
| c61 | | Thomas Kropf: Software Bugs Seen from an Industrial Perspective or Can Formal Methods Help on Automotive Software Development? CAV 2007: 3 |
| c60 | | Pradeep Kumar Nalla, Jörg Behrend, Prakash Mohan Peranandam, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel: Grid Based Fast Falsification For Bounded Property Checking. FDL 2007: 299-304 |
| c59 | | Djones Lettnin, Markus Winterholer, Axel G. Braun, Joachim Gerlach, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel: Coverage Driven Verification applied to Embedded Software. ISVLSI 2007: 159-164 |
| c58 | | Djones Lettnin, Pradeep Kumar Nalla, Jürgen Ruf, Roland J. Weiss, Axel G. Braun, Joachim Gerlach, Thomas Kropf, Wolfgang Rosenstiel: Semiformal Verification of Temporal Properties in Embedded Software. MBMV 2007: 19-28 |
| c57 | | Stefan Lämmermann, Jörg Behrend, Roland J. Weiss, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel: UML/SysML-Systemanalyse zur Generierung von formalen Verifikationseigenschaften für verschiedene Abstraktionsebenen. MBMV 2007: 29-38 |
| 2006 | ||
| j7 | | Pradeep Kumar Nalla, Roland J. Weiss, Prakash Mohan Peranandam, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel: Distributed Symbolic Bounded Property Checking. Electr. Notes Theor. Comput. Sci. 135(2): 47-63 (2006) |
| c56 | | Prakash Mohan Peranandam, Pradeep Kumar Nalla, Jürgen Ruf, Roland J. Weiss, Thomas Kropf, Wolfgang Rosenstiel: Fast falsification based on symbolic bounded property checking. DAC 2006: 1077-1082 |
| c55 | | Paul Duplys, Roland J. Weiss, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel: Monitoring-based Formal Hardware Verification. MBMV 2006: 217-221 |
| c54 | | Stefan Lämmermann, Roland J. Weiss, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel: Automatische Eigenschaftsextraktion auf Systemebene aus SystemC Modellen. MBMV 2006: 222-226 |
| 2005 | ||
| c53 | | Roland J. Weiss, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel: Efficient and Customizable Integration of Temporal Properties. FDL 2005: 385-397 |
| c52 | | Prakash Mohan Peranandam, Pradeep Kumar Nalla, Roland J. Weiss, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel: Overlap reduction in symbolic system traversal. HLDVT 2005: 145-152 |
| 2004 | ||
| c51 | | Jürgen Ruf, Roland J. Weiss, Thomas Kropf, Wolfgang Rosenstiel: Modeling and Formal Verification of Production Automation Systems. SoftSpez Final Report 2004: 541-566 |
| c50 | | Prakash Mohan Peranandam, Roland J. Weiss, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel: Dynamic guiding of bounded property checking. HLDVT 2004: 15-18 |
| c49 | | Prakash Mohan Peranandam, Roland J. Weiss, Jürgen Ruf, Thomas Kropf: Transactional Level Verification and Coverage Metrics by Means of Symbolic Simulation. MBMV 2004: 260-269 |
| 2003 | ||
| j6 | | Jürgen Ruf, Thomas Kropf: Symbolic Verification and Analysis of Discrete Timed Systems. Formal Methods in System Design 23(1): 67-108 (2003) |
| c48 | | Jürgen Ruf, Prakash Mohan Peranandam, Thomas Kropf, Wolfgang Rosenstiel: Using Symbolic Simulation for Bounded Property Checking. FDL 2003: 374-385 |
| 2002 | ||
| c47 | | |
| c46 | | Jürgen Ruf, Thomas Kropf, Jochen Klose: A Visual Approach to Validating System Level Designs. ISSS 2002: 186-191 |
| c45 | | |
| 2001 | ||
| j5 | | Jürgen Ruf, Thomas Kropf: Formale Verifikation diskreter Echtzeitsysteme (Formal Verification of Discrete Real-Time Systems). it+ti - Informationstechnik und Technische Informatik 43(1): 39-46 (2001) |
| c44 | | Jürgen Ruf, Dirk W. Hoffmann, Joachim Gerlach, Thomas Kropf, Wolfgang Rosenstiel, Wolfgang Müller: The simulation semantics of systemC. DATE 2001: 64-70 |
| c43 | | Jürgen Ruf, Dirk W. Hoffmann, Thomas Kropf, Wolfgang Rosenstiel: Simulation-guided property checking based on a multi-valued AR-automata. DATE 2001: 742-748 |
| 2000 | ||
| c42 | | |
| c41 | | Dirk W. Hoffmann, Thomas Kropf: Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits. DATE 2000: 758 |
| c40 | | Dirk W. Hoffmann, Thomas Kropf: Can Automatic Design Error Correction be Applied to Large Circuits? EUROMICRO 2000: 1114-1121 |
| c39 | | Dirk W. Hoffmann, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel: Simulation Meets Verification: Checking Temporal Properties in SystemC. EUROMICRO 2000: 1435- |
| c38 | | Jürgen Ruf, Dirk W. Hoffmann, Thomas Kropf, Wolfgang Rosenstiel: Checking temporal properties under simulation of executable system descriptions. HLDVT 2000: 161-166 |
| c37 | | Dirk W. Hoffmann, Thomas Kropf: Efficient Design Error Correction of Digital Circuits. ICCD 2000: 465-472 |
| 1999 | ||
| c36 | | Dirk W. Hoffmann, Thomas Kropf: Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction. CHARME 1999: 157-171 |
| c35 | | Jürgen Ruf, Thomas Kropf: Modleing and Checking Networks of Communicating Real-Time Process. CHARME 1999: 265-279 |
| c34 | | Michaela Huhn, Klaus Schneider, Thomas Kropf, George Logothetis: Verifying Imprecisely Working Arithmetic Circuits. DATE 1999: 65- |
| c33 | | |
| c32 | | Jürgen Ruf, Thomas Kropf: Modeling Real-Time Systems with I/O-Interval Structures. MBMV 1999: 91-100 |
| c31 | | Thomas Kropf: Recent Advancements in Hardware Verification - How to Make Theorem Proving Fit for an Industrial Usage. TPHOLs 1999: 1-4 |
| e3 | | Laurence Pierre, Thomas Kropf (Eds.): Correct Hardware Design and Verification Methods, 10th IFIP WG 10.5 Advanced Research Working Conference, CHARME '99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings. Lecture Notes in Computer Science 1703, Springer 1999, isbn 3-540-66559-5 |
| 1998 | ||
| c30 | | Ralf Reetz, Klaus Schneider, Thomas Kropf: Formal Specification in VHDL for Hardware Verification. DATE 1998: 257-263 |
| c29 | | Jürgen Ruf, Thomas Kropf: Using MTBDDs for Compostion and Model Checking of Real-Time Systems. FMCAD 1998: 185-202 |
| c28 | | Thomas Kropf, Jürgen Ruf, Klaus Schneider, Markus Wild: A Synchronous Language for Modeling and Verifying Real Time and Embedded Systems. MBMV 1998: 11-20 |
| 1997 | ||
| c27 | | Jürgen Ruf, Thomas Kropf: Symbolic model checking for a discrete clocked temporal logic with intervals. CHARME 1997: 146-163 |
| c26 | | Thomas Kropf, Jürgen Ruf: Using MTBDDs for discrete timed symbolic model checking. ED&TC 1997: 182-187 |
| c25 | | |
| c24 | | |
| c23 | | Jürgen Ruf, Thomas Kropf: A New Algorithm for Discrete Timed Symbolic Model Checking. HART 1997: 18-32 |
| e2 | | Thomas Kropf (Ed.): Formal Hardware Verification - Methods and Systems in Comparison. Lecture Notes in Computer Science 1287, Springer 1997, isbn 3-540-63475-4 |
| 1996 | ||
| c22 | | Klaus Schneider, Thomas Kropf: A Unified Approach for Combining Different Formalisms for Hardware Verification. FMCAD 1996: 202-217 |
| 1995 | ||
| j4 | | Oliver F. Haberl, Thomas Kropf: HIST: A hierarchical self test methodology for chips, boards, and systems. J. Electronic Testing 6(1): 85-106 (1995) |
| j3 | | Ralf Reetz, Thomas Kropf: A Flowgraph Semantics of VHDL: Toward a VHDL Verification Workbench in HOL. Formal Methods in System Design 7(1/2): 73-99 (1995) |
| c21 | | Ramayya Kumar, Thomas Kropf, Klaus Schneider: Formal synthesis of circuits with a simple handshake protocol. VLSI Design 1995: 255-259 |
| 1994 | ||
| j2 | | Klaus Schneider, Ramayya Kumar, Thomas Kropf: Accelerating Tableaux Proofs Using Compact Representations. Formal Methods in System Design 5(1/2): 145-176 (1994) |
| c20 | | Oliver F. Haberl, Thomas Kropf: Self Testable Boards with Standard IEEE 1149.5 Module Test and Maintenance (MTM) Bus Interface. EDAC-ETC-EUROASIC 1994: 220-225 |
| c19 | | Jürgen Frößl, Thomas Kropf: A New Model to Uniformly Represent the Function and Timing of MOS Circuits and its Application to VHDL Simulation. EDAC-ETC-EUROASIC 1994: 343-348 |
| c18 | | Klaus Schneider, Thomas Kropf, Ramayya Kumar: Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path. EDAC-ETC-EUROASIC 1994: 648-652 |
| c17 | | |
| c16 | | Thomas Kropf, Klaus Schneider, Ramayya Kumar: A Formal Framework for High Level Synthesis. TPCD 1994: 223-238 |
| c15 | | Ralf Reetz, Thomas Kropf: Simplifying Deep Embedding: A Formalised Code Generator. TPHOLs 1994: 378-390 |
| c14 | | Klaus Schneider, Ramayya Kumar, Thomas Kropf: Automating Verification by Functional Abstraction at the System Level. TPHOLs 1994: 391-406 |
| e1 | | Ramayya Kumar, Thomas Kropf (Eds.): Theorem Provers in Circuit Design - Theory, Practice and Experience, Second International Conference, TPCD '94, Bad Herrenalb, Germany, September 26-28, 1994, Proceedings. Lecture Notes in Computer Science 901, Springer 1994, isbn 3-540-59047-1 |
| 1993 | ||
| j1 | | Ramayya Kumar, Klaus Schneider, Thomas Kropf: Structuring and Automating Hardware Proofs in a Higher-Order Theorem-Proving Environment. Formal Methods in System Design 2(2): 165-223 (1993) |
| c13 | | Thomas Kropf, Ramayya Kumar, Klaus Schneider: Embedding Hardware Verification Within a Commercial Design Framework. CHARME 1993: 242-257 |
| c12 | | Klaus Schneider, Ramayya Kumar, Thomas Kropf: Hardware-Verification using First Order BDDs. CHDL 1993: 45-62 |
| c11 | | Klaus Schneider, Ramayya Kumar, Thomas Kropf: Alternative Proof Procedures for Finite-State Machines in Higher-Order Logic. HUG 1993: 213-226 |
| c10 | | Klaus Schneider, Ramayya Kumar, Thomas Kropf: Eliminating Higher-Order Quantifiers to Obtain Decision Procedures for Hardware Verification. HUG 1993: 385-398 |
| 1992 | ||
| c9 | | |
| c8 | | Oliver F. Haberl, Thomas Kropf: HIST: A Methodology for the Automatic Insertion of a Hierarchical Self Test. ITC 1992: 732-741 |
| c7 | | Klaus Schneider, Ramayya Kumar, Thomas Kropf: Efficient Representation and Computation of Tableau Proofs. TPHOLs 1992: 39-57 |
| c6 | | Klaus Schneider, Ramayya Kumar, Thomas Kropf: Modelling Generic Hardware Structures by Abstract Datatypes. TPHOLs 1992: 165-175 |
| 1991 | ||
| c5 | | Klaus Schneider, Ramayya Kumar, Thomas Kropf: Automating Most Parts of Hardware Proofs in HOL. CAV 1991: 365-375 |
| c4 | | Thomas Kropf, Hans-Joachim Wunderlich: A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic. ITC 1991: 57-66 |
| c3 | | Ramayya Kumar, Thomas Kropf, Klaus Schneider: Integrating a First-Order Automatic Prover in the HOL Environment. TPHOLs 1991: 170-176 |
| c2 | | Ramayya Kumar, Thomas Kropf, Klaus Schneider: First Steps Towards Automating Hardware Proofs in HOL. TPHOLs 1991: 190-193 |
| c1 | | Klaus Schneider, Ramayya Kumar, Thomas Kropf: Structurein Hardware Proofs: Fist Steps Towards Automation in a Higher-Order Environment. VLSI 1991: 81-90 |
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