Reiner Kolla

Marcel Baunach, Reiner Kolla, Clemens Muhlberger: A Method for Self-Organizing Communication in WSN Based Localization Systems: HashSlot. LCN 2007: 825-832

Marcel Baunach, Reiner Kolla, Clemens Muhlberger: Beyond Theory: Development of a Real World Localization Application as Low Power WSN. LCN 2007: 872-884

Frank Wolz, Reiner Kolla: Disproving the Perfect-Rate Property of Data-Flow Graphs Unfolded by the Least Common Multiple of the Number of Loop Registers. IEEE Trans. Computers 52(5): 688 (2003)

Frank Wolz, Reiner Kolla: A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures. FPL 2002: 997-1006

Frank Wolz, Reiner Kolla: Bubble Partitioning for LUT-Based Sequential Circuits. FPL 2001: 336-345

Reiner Kolla: Technology Binding. Informatik Spektrum 23(3): 212-215 (2000)

Frank Wolz, Reiner Kolla: A New Floorplanning Method for FPGA Architectural Research. FPL 2000: 432-442

Reiner Kolla, A. Vodopivec, Jürgen Wolff von Gudenberg: Splitting Double Precision FPUs for Single Precision Interval Arithmetic. ARCS Workshops 1999: 5-16

Winfried Nöth, Reiner Kolla: Spanning Tree-based State Encoding for Low Power Dissipation. DATE 1999: 168-174

Uwe Hinsberger, Reiner Kolla: Boolean Matching for Large Libraries. DAC 1998: 206-211

Reiner Kolla, Oliver Springauf: PACE: Processor Architectures for Circuit Emulation. IPPS/SPDP Workshops 1998: 105-110

Uwe Hinsberger, Reiner Kolla, Markus Wild: A parallel hybrid approach to hard optimization problems. ARCS 1997: 201-210

Winfried Nöth, Reiner Kolla: Node normalization and decomposition in low power technology mapping. ISLPED 1997: 275-280

Winfried Nöth, Uwe Hinsberger, Reiner Kolla: TROY: A Tree-Based Approach to Logic Synthesis and Technology Mapping. Great Lakes Symposium on VLSI 1996: 188-193

Uwe Hinsberger, Reiner Kolla: Optimal technology mapping for single output cells. Great Lakes Symposium on VLSI 1995: 14-

Uwe Hinsberger, Reiner Kolla: A cell-based approach to performance optimization of fanout-free circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 11(10): 1317-1322 (1992)

Reiner Kolla, Bernd Serf: The Virtual Feedback Problem in Hierarchical Representations of Combinational Circuits. Acta Inf. 28(5): 463-476 (1991)

Reiner Kolla: Minimal Area Sizing of Power Supply Nets in VLSI Circuits. Elektronische Informationsverarbeitung und Kybernetik 26(11/12): 585-605 (1990)

Bernd Becker, Thomas Burch, Günter Hotz, D. Kiel, Reiner Kolla, Paul Molitor, Hans-Georg Osthof, Gisela Pitsch, Uwe Sparmann: A graphical system for hierarchical specifications and checkups of VLSI circuits. EURO-DAC 1990: 174-179

Uwe Hinsberger, Reiner Kolla: Cell based performance optimization of combinational circuits. EURO-DAC 1990: 594-599

Reiner Kolla: A dynamic programming approach to the power supply net sizing problem. EURO-DAC 1990: 600-604

Reiner Kolla, Paul Molitor, Hans-Georg Osthof: Einführung in den VLSI-Entwurf. Leitfäden und Monographien der Informatik, Teubner 1989, isbn 978-3-519-02273-2, pp. 1-352

Bernd Becker, Reiner Kolla: On the Construction of Optimal Time Adders (Extended Abstract). STACS 1988: 18-28

Bernd Becker, Günter Hotz, Reiner Kolla, Paul Molitor, Hans-Georg Osthof: Hierarchical Design Based on a Calculus of Nets. DAC 1987: 649-653

Günter Hotz, Bernd Becker, Reiner Kolla, Paul Molitor: Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil I. Inform., Forsch. Entwickl. 1(1): 38-47 (1986)

Günter Hotz, Bernd Becker, Reiner Kolla, Paul Molitor: Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil II. Inform., Forsch. Entwickl. 1(2): 72-82 (1986)

Günter Hotz, Reiner Kolla, Paul Molitor: On Network Algebras and Recursive Equations. Graph-Grammars and Their Application to Computer Science 1986: 250-261

Reiner Kolla: Where-Oblivious is not Sufficient. Inf. Process. Lett. 17(5): 263-268 (1983)