Please note: This is a beta version of the new dblp website.
You can find the classic dblp view of this page here.
You can find the classic dblp view of this page here.
Taewhan Kim
2010 – today
- 2013
[j53]Jongyoon Jung, Taewhan Kim: Statistical Viability Analysis for Detecting False Paths Under Delay Variation. IEEE Trans. on CAD of Integrated Circuits and Systems 32(1): 111-123 (2013)- [j52]Tak-Yung Kim, Taewhan Kim: Resource Allocation and Design Techniques of Prebond Testable 3-D Clock Tree. IEEE Trans. on CAD of Integrated Circuits and Systems 32(1): 138-151 (2013)
- [j51]Kyoung-Hwan Lim, Deokjin Joo, Taewhan Kim: An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 32(3): 392-405 (2013)
- [c62]Juyeon Kim, Deokjin Joo, Taewhan Kim: An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem. DAC 2013: 90
- 2012
- [j50]Hyungjung Seo, Jaewon Seo, Taewhan Kim: Algorithms for Combined Inter- and Intra-Task Dynamic Voltage Scaling. Comput. J. 55(11): 1367-1382 (2012)
- [j49]Deokjin Joo, Minseok Kang, Taewhan Kim: Design Methodologies for Reliable Clock Networks. JCSE 6(4): 257-266 (2012)
- [j48]Jongyoon Jung, Taewhan Kim: Variation-Aware False Path Analysis Based on Statistical Dynamic Timing Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 31(11): 1684-1697 (2012)
- [j47]YongHwan Kim, Sanghoon Kwak, Taewhan Kim: Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint. ACM Trans. Design Autom. Electr. Syst. 17(4): 43 (2012)
- [c61]Kiyoung Kim, Taewhan Kim: Algorithm for synthesizing design context-aware fast carry-skip adders. ASP-DAC 2012: 795-800
- 2011
- [j46]Hochang Jang, Deokjin Joo, Taewhan Kim: Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 30(1): 96-109 (2011)
- [j45]Tak-Yung Kim, Taewhan Kim: Clock Tree synthesis for TSV-based 3D IC designs. ACM Trans. Design Autom. Electr. Syst. 16(4): 48 (2011)
- [j44]Jongyoon Jung, Taewhan Kim: Scheduling and Resource Binding Algorithm Considering Timing Variation. IEEE Trans. VLSI Syst. 19(2): 205-216 (2011)
- [j43]Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim: Comprehensive Analysis and Control of Design Parameters for Power Gated Circuits. IEEE Trans. VLSI Syst. 19(3): 494-498 (2011)
- [c60]Kyoung-Hwan Lim, Taewhan Kim: An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. ASP-DAC 2011: 503-508
- [c59]Yongho Lee, Taewhan Kim: A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs. ASP-DAC 2011: 603-608
- [c58]Deokjin Joo, Taewhan Kim: WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing. DAC 2011: 522-527
- 2010
- [j42]HaNeul Chon, Taewhan Kim: Resource Sharing Problem of Timing Variation-Aware Task Scheduling and Binding in MPSoC. Comput. J. 53(7): 883-894 (2010)
- [j41]Taewhan Kim: Task-Level Dynamic Voltage Scaling for Embedded System Design: Recent Theoretical Results. JCSE 4(3): 189-206 (2010)
- [j40]Seungwhun Paik, Insup Shin, Taewhan Kim, Youngsoo Shin: HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 657-670 (2010)
- [c57]Yongho Lee, Taewhan Kim: Technique for controlling power-mode transition noise in distributed sleep transistor network. ASP-DAC 2010: 131-136
- [c56]
- [c55]Tak-Yung Kim, Taewhan Kim: Clock tree synthesis with pre-bond testability for 3D stacked IC designs. DAC 2010: 723-728
- [c54]Tak-Yung Kim, Taewhan Kim: Bounded skew clock routing for 3D stacked IC designs: Enabling trade-offs between power and clock skew. Green Computing Conference 2010: 525-532
- [c53]Danbee Park, Jungseob Lee, Nam Sung Kim, Taewhan Kim: Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors. ICCAD 2010: 361-364
- [c52]Minseok Kang, Taewhan Kim: Clock buffer polarity assignment considering the effect of delay variations. ISQED 2010: 69-74
2000 – 2009
- 2009
- [j39]Benjamin Carrión Schäfer, Taewhan Kim: Autonomous temperature control technique in VLSI circuits through logic replication. IET Computers & Digital Techniques 3(1): 62-71 (2009)
- [j38]Kyoung-Hwan Lim, YongHwan Kim, Taewhan Kim: Interconnect and communication synthesis for distributed register-file microarchitecture. IET Computers & Digital Techniques 3(2): 162-174 (2009)
- [j37]Pilok Lim, Ki-Seok Chung, Taewhan Kim: Thermal-Aware High-Level Synthesis Based on Network Flow Method. Journal of Circuits, Systems, and Computers 18(5): 965-984 (2009)
- [j36]ByungHyun Lee, Ki-Seok Chung, Bontae Koo, Nak-Woong Eum, Taewhan Kim: Thermal sensor allocation and placement for reconfigurable systems. ACM Trans. Design Autom. Electr. Syst. 14(4) (2009)
- [c51]HaNeul Chon, Taewhan Kim: Timing variation-aware task scheduling and binding for MPSoC. ASP-DAC 2009: 137-142
- [c50]Hochang Jang, Taewhan Kim: Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization. DAC 2009: 794-799
- [c49]Jongyoon Jung, Taewhan Kim: Timing variation-aware high-level synthesis considering accurate yield computation. ICCD 2009: 207-212
- 2008
- [j35]Soonhoi Ha, Kiyoung Choi, Taewhan Kim, Krisztián Flautner, Sang Lyul Min, Wang Yi: Introduction to embedded systems week 2006 special issue. ACM Trans. Embedded Comput. Syst. 7(2) (2008)
- [j34]Benjamin Carrión Schäfer, Taewhan Kim: Hotspots Elimination and Temperature Flattening in VLSI Circuits. IEEE Trans. VLSI Syst. 16(11): 1475-1487 (2008)
- [c48]ByungHyun Lee, Taewhan Kim: Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension. ASP-DAC 2008: 703-707
- [c47]Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim: Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits. ICCAD 2008: 169-172
- [c46]Yesin Ryu, Taewhan Kim: Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization. ICCAD 2008: 416-419
- [c45]Eunjoo Choi, Changsik Shin, Taewhan Kim, Youngsoo Shin: Power-gating-aware high-level synthesis. ISLPED 2008: 39-44
- 2007
- [j33]Taewhan Kim, Jungeun Kim: Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 142-151 (2007)
- [j32]Yongseok Choi, Naehyuck Chang, Taewhan Kim: DC-DC Converter-Aware Power Management for Low-Power Embedded Systems. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1367-1381 (2007)
- [c44]Kyoung-Hwan Lim, YongHwan Kim, Taewhan Kim: Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture. DAC 2007: 765-770
- [c43]
- [c42]Zhenmin Li, Taewhan Kim: Address Code Optimization Exploiting Code Scheduling in DSP Applications. ISCAS 2007: 1573-1576
- [c41]Benjamin Carrión Schäfer, Yongho Lee, Taewhan Kim: Temperature-Aware Compilation for VLIWProcessors. RTCSA 2007: 426-431
- [e2]Taewhan Kim, Pascal Sainrat, Steven S. Lumetta, Nacho Navarro (Eds.): Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007. ACM 2007
- 2006
- [j31]Yoonseo Choi, Taewhan Kim: Memory Access Driven Storage Assignment for Variables in Embedded System Design. Journal of Circuits, Systems, and Computers 15(2): 145-168 (2006)
- [j30]Jaewon Seo, Taewhan Kim, Joonwon Lee: Optimal intratask dynamic voltage-scaling technique and its practical extensions. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 47-57 (2006)
- [j29]Junhyung Um, Taewhan Kim: Resource Sharing Combined with Layout Effects in High-Level Synthesis. VLSI Signal Processing 44(3): 231-243 (2006)
- [j28]Young-Jun Kim, Taewhan Kim: A HW/SW Partitioner for Multi-Mode Multi-Task Embedded Applications. VLSI Signal Processing 44(3): 269-283 (2006)
- [c40]Pilok Lim, Taewhan Kim: Thermal-aware high-level synthesis based on network flow method. CODES+ISSS 2006: 124-129
- [c39]Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-Taek Kim, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, Taewhan Kim: A systematic IP and bus subsystem modeling for platform-based system design. DATE 2006: 560-564
- [c38]Young-Jun Kim, Taewhan Kim: HW/SW partitioning techniques for multi-mode multi-task embedded applications. ACM Great Lakes Symposium on VLSI 2006: 25-30
- [c37]Taewhan Kim: Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling. RTCSA 2006: 199-206
- [e1]Seongsoo Hong, Wayne Wolf, Krisztián Flautner, Taewhan Kim (Eds.): Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006. ACM 2006, ISBN 1-59593-543-6
- 2005
- [j27]Yoonseo Choi, Taewhan Kim, Hwansoo Han: Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 278-287 (2005)
- [j26]Woo-Cheol Kwon, Taewhan Kim: Optimal voltage allocation techniques for dynamically variable voltage processors. ACM Trans. Embedded Comput. Syst. 4(1): 211-230 (2005)
- [c36]Jungeun Kim, Taewhan Kim: Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design. DAC 2005: 105-110
- [c35]Yongseok Choi, Naehyuck Chang, Taewhan Kim: DC-DC converter-aware power management for battery-operated embedded systems. DAC 2005: 895-900
- [c34]Jaewon Seo, Taewhan Kim, Nikil D. Dutt: Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications. ICCAD 2005: 450-455
- 2004
- [j25]Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung: CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation. IEEE Trans. Computers 53(7): 829-842 (2004)
- [j24]Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim: Coupling-aware high-level interconnect synthesis [IC layout]. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 157-164 (2004)
- [j23]Keoncheol Shin, Taewhan Kim: Tight integration of timing-driven synthesis and placement of parallel multiplier circuits. IEEE Trans. VLSI Syst. 12(7): 766-775 (2004)
- [c33]Keoncheol Shin, Taewhan Kim: An integrated approach to timing-driven synthesis and placement of arithmetic circuits. ASP-DAC 2004: 155-158
- [c32]Yoonseo Choi, Taewhan Kim: Memory access driven storage assignment for variables in embedded system design. ASP-DAC 2004: 478-481
- [c31]Meeyoung Cha, Chun-Gi Lyuh, Taewhan Kim: Resource-constrained low-power bus encoding with crosstalk delay elimination. ASP-DAC 2004: 834-837
- [c30]Chun-Gi Lyuh, Taewhan Kim: Memory access scheduling and binding considering energy minimization in multi-bank memory systems. DAC 2004: 81-86
- [c29]Jaewon Seo, Taewhan Kim, Ki-Seok Chung: Profile-based optimal intra-task voltage scheduling for hard real-time applications. DAC 2004: 87-92
- [c28]Keoncheol Shin, Taewhan Kim: Leakage power minimization for the synthesis of parallel multiplier circuits. ACM Great Lakes Symposium on VLSI 2004: 166-169
- 2003
- [j22]Sungpack Hong, Taewhan Kim: Bus Optimization for Low Power in High-Level Synthesis. Journal of Circuits, Systems, and Computers 12(1): 1-18 (2003)
- [j21]Yoonseo Choi, Taewhan Kim: Address assignment in DSP code generation - an integrated approach. IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 976-984 (2003)
- [j20]Junhyung Um, Taewhan Kim: Synthesis of arithmetic circuits considering layout effects. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1487-1503 (2003)
- [j19]Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang: Minimum delay optimization for domino circuits - a coupling-aware approach. ACM Trans. Design Autom. Electr. Syst. 8(2): 202-213 (2003)
- [j18]Chun-Gi Lyuh, Taewhan Kim: High-level synthesis for low power based on network flow method. IEEE Trans. VLSI Syst. 11(3): 364-375 (2003)
- [j17]Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang: Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. VLSI Syst. 11(5): 879-887 (2003)
- [j16]Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda: Memory allocation and mapping in high-level synthesis - an integrated approach. IEEE Trans. VLSI Syst. 11(5): 928-938 (2003)
- [c27]Woo-Cheol Kwon, Taewhan Kim: Optimal voltage allocation techniques for dynamically variable voltage processors. DAC 2003: 125-130
- [c26]Yoonseo Choi, Taewhan Kim: Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. DAC 2003: 881-886
- [c25]Junhyung Um, Taewhan Kim: Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design. ICCAD 2003: 197-200
- 2002
- [j15]Ki-Seok Chung, Taewhan Kim, C. L. Liu: A Complete Model for Glitch Analysis in Logic Circuits. Journal of Circuits, Systems, and Computers 11(2): 137-154 (2002)
- [j14]Yoonseo Choi, Taewhan Kim: Binding Algorithm for Power Optimization Based on Network Flow Method. Journal of Circuits, Systems, and Computers 11(3): 259-272 (2002)
- [j13]Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang: Domino logic synthesis based on implication graph. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 232-240 (2002)
- [j12]Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu: Logic transformation for low-power synthesis. ACM Trans. Design Autom. Electr. Syst. 7(2): 265-283 (2002)
- [j11]Ki-Seok Chung, Rajesh K. Gupta, Taewhan Kim, C. L. Liu: Synthesis and Optimization of Combinational Interface Circuits. VLSI Signal Processing 31(3): 243-261 (2002)
- [c24]
- [c23]Yoonseo Choi, Taewhan Kim: Address assignment combined with scheduling in DSP code generation. DAC 2002: 225-230
- [c22]Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda: An integrated algorithm for memory allocation and assignment in high-level synthesis. DAC 2002: 608-611
- [c21]Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim: Coupling-aware high-level interconnect synthesis for low power. ICCAD 2002: 609-613
- [c20]Junhyung Um, Jae-hoon Kim, Taewhan Kim: Layout-driven resource sharing in high-level synthesis. ICCAD 2002: 614-618
- [c19]Unni Narayanan, Ki-Seok Chung, Taewhan Kim: Enhanced bus invert encodings for low-power. ISCAS (5) 2002: 25-28
- [c18]Jaewon Seo, Taewhan Kim: Memory exploration utilizing scheduling effects in high-level synthesis. ISCAS (4) 2002: 73-76
- [c17]Yoonseo Choi, Taewhan Kim: An efficient low-power binding algorithm in high-level synthesis. ISCAS (4) 2002: 321-324
- [c16]Yoonseo Choi, Taewhan Kim: Address code optimization using code scheduling for digital signal processors. ISCAS (5) 2002: 481-484
- 2001
- [j10]Junhyung Um, Taewhan Kim: An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits. IEEE Trans. Computers 50(3): 215-233 (2001)
- [j9]Ki-Seok Chung, Taewhan Kim, C. L. Liu: G-vector: A New Model for Glitch Analysis in Logic Circuits. VLSI Signal Processing 27(3): 235-251 (2001)
- [c15]Youngtae Kim, Taewhan Kim: Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders. ASP-DAC 2001: 622-628
- [c14]Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu: A Static Estimation Technique of Power Sensitivity in Logic Circuits. DAC 2001: 215-219
- [c13]Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung: An accurate evaluation of routing density for symmetrical FPGAs. ACM Great Lakes Symposium on VLSI 2001: 51-55
- [c12]Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation. ICCAD 2001: 137-143
- [c11]Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu: An Integrated Data Path Optimization for Low Power Based on Network Flow Method. ICCAD 2001: 553-559
- 2000
- [j8]Sungpack Hong, Taewhan Kim, Unni Narayanan, Ki-Seok Chung: Decomposition of Bus-Invert Coding for Low-Power I/O. Journal of Circuits, Systems, and Computers 10(1-2): 101-112 (2000)
- [j7]Youngtae Kim, Taewhan Kim: An Accurate Exploration of Timing and Area Trade-Offs in Arithmetic Optimization Using Carry-Save-Adders. Journal of Circuits, Systems, and Computers 10(5-6): 279-292 (2000)
- [j6]Taewhan Kim, Junhyung Um: A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders. IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 615-624 (2000)
- [c10]Taewhan Kim, Junhyung Um: A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper). ASP-DAC 2000: 313-316
- [c9]Junhyung Um, Taewhan Kim, C. L. Liu: A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. DAC 2000: 98-103
- [c8]Ki-Seok Chung, Taewhan Kim, Chien-Liang Liu: Behavioral-level partitioning for low power design in control-dominated application. ACM Great Lakes Symposium on VLSI 2000: 156-161
- [c7]Gernot Koch, Taewhan Kim, Reiner Genevriere: A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis. ICCAD 2000: 33-38
- [c6]Sungpack Hong, Taewhan Kim: Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method. ICCAD 2000: 312-317
1990 – 1999
- 1999
- [c5]Junhyung Um, Taewhan Kim, C. L. Liu: Optimal allocation of carry-save-adders in arithmetic optimization. ICCAD 1999: 410-413
- 1998
- [j5]Taewhan Kim, William Jao, Steven W. K. Tjiang: Circuit optimization using carry-save-adder cells. IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 974-984 (1998)
- [j4]Chaeryung Park, Taewhan Kim, C. L. Liu: Register Allocation - A Hierarchical Reduction Approach. VLSI Signal Processing 19(3): 269-285 (1998)
- [c4]Taewhan Kim, William Jao, Steven W. K. Tjiang: Arithmetic Optimization Using Carry-Save-Adders. DAC 1998: 433-438
- 1996
- [j3]Taewhan Kim, C. L. Liu: An integrated algorithm for incremental data path synthesis. VLSI Signal Processing 12(3): 265-285 (1996)
- 1995
- [j2]Taewhan Kim, C. L. Liu: A new approach to the multiport memory allocation problem in data path synthesis. Integration 19(3): 133-160 (1995)
- 1994
- [j1]Taewhan Kim, Noritake Yonezawa, Jane W.-S. Liu, C. L. Liu: A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach. IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 425-438 (1994)
- [c3]Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu: A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability. EDAC-ETC-EUROASIC 1994: 586-590
- 1993
- [c2]
- 1991
- [c1]Taewhan Kim, Jane W.-S. Liu, C. L. Liu: A Scheduling Algorithm for Conditional Resource Sharing. ICCAD 1991: 84-87
Coauthor Index
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2013-05-29 01:52 CEST by the dblp team