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Semantic ScholarStephen W. Keckler
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- affiliation: University of Texas at Austin, USA
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2010 – today
- 2018
[c84]Minsoo Rhu, Mike O'Connor, Niladrish Chatterjee, Jeff Pool, Youngeun Kwon, Stephen W. Keckler:
Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks. HPCA 2018: 78-91- 2017
- [c83]Niladrish Chatterjee, Mike O'Connor, Donghyuk Lee, Daniel R. Johnson, Stephen W. Keckler, Minsoo Rhu, William J. Dally:
Architecting an Energy-Efficient DRAM System for GPUs. HPCA 2017: 73-84 - [c82]Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally:
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. ISCA 2017: 27-40 - [c81]Siva Kumar Sastry Hari, Timothy Tsai, Mark Stephenson, Stephen W. Keckler, Joel S. Emer:
SASSIFI: An architecture-level fault injection tool for GPU application resilience evaluation. ISPASS 2017: 249-258 - [c80]Mike O'Connor, Niladrish Chatterjee, Donghyuk Lee, John M. Wilson, Aditya Agrawal, Stephen W. Keckler, William J. Dally:
Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems. MICRO 2017: 41-54 - [c79]Guanpeng Li, Siva Kumar Sastry Hari, Michael Sullivan, Timothy Tsai, Karthik Pattabiraman, Joel S. Emer, Stephen W. Keckler:
Understanding error propagation in deep learning neural network (DNN) accelerators and applications. SC 2017: 8:1-8:12 - [i3]Minsoo Rhu, Mike O'Connor, Niladrish Chatterjee, Jeff Pool, Stephen W. Keckler:
Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks. CoRR abs/1705.01626 (2017) - [i2]Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally:
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. CoRR abs/1708.04485 (2017) - 2016
- [c78]Injoon Hong, Jason Clemons, Rangharajan Venkatesan, Iuri Frosio, Brucek Khailany, Stephen W. Keckler:
A real-time energy-efficient superpixel hardware accelerator for mobile computer vision applications. DAC 2016: 95:1-95:6 - [c77]Gennady Pekhimenko, Evgeny Bolotin, Nandita Vijaykumar, Onur Mutlu, Todd C. Mowry, Stephen W. Keckler:
A case for toggle-aware compression for GPU systems. HPCA 2016: 188-200 - [c76]Tianhao Zheng, David W. Nellans, Arslan Zulfiqar, Mark Stephenson, Stephen W. Keckler:
Towards high performance paged memory for GPUs. HPCA 2016: 345-357 - [c75]Neha Agarwal, David W. Nellans, Eiman Ebrahimi, Thomas F. Wenisch, John Danskin, Stephen W. Keckler:
Selective GPU caches to eliminate CPU-GPU HW cache coherence. HPCA 2016: 494-506 - [c74]Kevin Hsieh, Eiman Ebrahimi, Gwangsun Kim, Niladrish Chatterjee, Mike O'Connor, Nandita Vijaykumar, Onur Mutlu, Stephen W. Keckler:
Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems. ISCA 2016: 204-216 - [c73]Aditya Agrawal, Mike O'Connor, Evgeny Bolotin, Niladrish Chatterjee, Joel S. Emer, Stephen W. Keckler:
CLARA: Circular Linked-List Auto and Self Refresh Architecture. MEMSYS 2016: 338-349 - [c72]Minsoo Rhu, Natalia Gimelshein, Jason Clemons, Arslan Zulfiqar, Stephen W. Keckler:
vDNN: Virtualized deep neural networks for scalable, memory-efficient neural network design. MICRO 2016: 18:1-18:13 - [c71]Jason Clemons, Chih-Chi Cheng, Iuri Frosio, Daniel R. Johnson, Stephen W. Keckler:
A patch memory system for image processing and computer vision. MICRO 2016: 51:1-51:13 - [i1]Minsoo Rhu, Natalia Gimelshein, Jason Clemons, Arslan Zulfiqar, Stephen W. Keckler:
Virtualizing Deep Neural Networks for Memory-Efficient Neural Network Design. CoRR abs/1602.08124 (2016) - 2015
- [j26]Gennady Pekhimenko, Evgeny Bolotin, Mike O'Connor, Onur Mutlu, Todd C. Mowry, Stephen W. Keckler:
Toggle-Aware Compression for GPUs. Computer Architecture Letters 14(2): 164-168 (2015) - [j25]Stephen W. Keckler:
Increasing Interconnection Network Throughput with Virtual Channels. IEEE Computer 48(7): 10 (2015) - [j24]Evgeny Bolotin, David W. Nellans, Oreste Villa, Mike O'Connor, Alex Ramírez, Stephen W. Keckler:
Designing Efficient Heterogeneous Memory Architectures. IEEE Micro 35(4): 60-68 (2015) - [c70]Neha Agarwal, David W. Nellans, Mark Stephenson, Mike O'Connor, Stephen W. Keckler:
Page Placement Strategies for GPUs within Heterogeneous Memory Systems. ASPLOS 2015: 607-618 - [c69]Neha Agarwal, David W. Nellans, Mike O'Connor, Stephen W. Keckler, Thomas F. Wenisch:
Unlocking bandwidth for GPUs in CC-NUMA systems. HPCA 2015: 354-365 - [c68]Joel Hestness, Stephen W. Keckler, David A. Wood:
GPU Computing Pipeline Inefficiencies and Optimization Opportunities in Heterogeneous CPU-GPU Processors. IISWC 2015: 87-97 - [c67]Mark Stephenson, Siva Kumar Sastry Hari, Yunsup Lee, Eiman Ebrahimi, Daniel R. Johnson, David W. Nellans, Mike O'Connor, Stephen W. Keckler:
Flexible software profiling of GPU architectures. ISCA 2015: 185-197 - [c66]Timothy G. Rogers, Daniel R. Johnson, Mike O'Connor, Stephen W. Keckler:
A variable warp size architecture. ISCA 2015: 489-501 - [c65]Adwait Jog, Onur Kayiran, Tuba Kesten, Ashutosh Pattnaik, Evgeny Bolotin, Niladrish Chatterjee, Stephen W. Keckler, Mahmut T. Kandemir, Chita R. Das:
Anatomy of GPU Memory System for Multi-Application Execution. MEMSYS 2015: 223-234 - 2014
- [j23]Stephen W. Keckler:
Rethinking caches for throughput processors: technical perspective. Commun. ACM 57(12): 90 (2014) - [j22]Stephen W. Keckler, Dean M. Tullsen:
2014 International Symposium on Computer Architecture Influential Paper Award; 2014 Maurice Wilkes Award Given to Ravi Rajwar. IEEE Micro 34(6): 95-97 (2014) - [j21]Madhu Saravana Sibi Govindan, Behnam Robatmili, Dong Li, Bertrand A. Maher, Aaron Smith, Stephen W. Keckler, Doug Burger:
Scaling Power and Performance viaProcessor Composability. IEEE Trans. Computers 63(8): 2025-2038 (2014) - [c64]Adwait Jog, Evgeny Bolotin, Zvika Guz, Mike Parker, Stephen W. Keckler, Mahmut T. Kandemir, Chita R. Das:
Application-aware Memory System for Fair and Efficient Execution of Concurrent GPGPU Applications. GPGPU@ASPLOS 2014: 1 - [c63]Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang, Doug Burger, Stephen W. Keckler:
Author retrospective for a NUCA substrate for flexible CMP cache sharing. ICS 25th Anniversary 2014: 74-76 - [c62]Joel Hestness, Stephen W. Keckler, David A. Wood:
A comparative analysis of microarchitecture effects on CPU and GPU memory system behavior. IISWC 2014: 150-160 - [c61]Yunsup Lee, Vinod Grover, Ronny Krashinsky, Mark Stephenson, Stephen W. Keckler, Krste Asanovic:
Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures. MICRO 2014: 101-113 - [c60]Jeffrey R. Diamond, Donald S. Fussell, Stephen W. Keckler:
Arbitrary Modulus Indexing. MICRO 2014: 140-152 - [c59]Oreste Villa, Daniel R. Johnson, Mike O'Connor, Evgeny Bolotin, David W. Nellans, Justin Luitjens, Nikolai Sakharnykh, Peng Wang, Paulius Micikevicius, Anthony Scudiero, Stephen W. Keckler, William J. Dally:
Scaling the Power Wall: A Path to Exascale. SC 2014: 830-841 - 2013
- [c58]Yunsup Lee, Ronny Krashinsky, Vinod Grover, Stephen W. Keckler, Krste Asanovic:
Convergence and scalarization for data-parallel architectures. CGO 2013: 32:1-32:11 - [c57]William J. Dally, Chris Malachowsky, Stephen W. Keckler:
21st century digital design tools. DAC 2013: 94:1-94:6 - [c56]Behnam Robatmili, Dong Li, Hadi Esmaeilzadeh, Madhu Saravana Sibi Govindan, Aaron Smith, Andrew Putnam, Doug Burger, Stephen W. Keckler:
How to implement effective prediction and forwarding for fusable dynamic multicore architectures. HPCA 2013: 460-471 - 2012
- [j20]Stephen W. Keckler, Steven K. Reinhardt:
Massively Multithreaded Computing Systems. IEEE Computer 45(8): 24-25 (2012) - [j19]Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu:
A QoS-Enabled On-Die Interconnect Fabric for Kilo-Node Chips. IEEE Micro 32(3): 17-25 (2012) - [j18]Doug Burger, Stephen W. Keckler, Mark Papermaster:
Charles R. (Chuck) Moore (1961 - 2012). IEEE Micro 32(4): 3-5 (2012) - [j17]Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron:
A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors. ACM Trans. Comput. Syst. 30(2): 8:1-8:38 (2012) - [c55]Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger:
Exploiting microarchitectural redundancy for defect tolerance. ICCD 2012: 35-42 - [c54]Mark Gebhart, Stephen W. Keckler, Brucek Khailany, Ronny Krashinsky, William J. Dally:
Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor. MICRO 2012: 96-106 - 2011
- [j16]Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco:
GPUs and the Future of Parallel Computing. IEEE Micro 31(5): 7-17 (2011) - [c53]Behnam Robatmili, Madhu Saravana Sibi Govindan, Doug Burger, Stephen W. Keckler:
Exploiting criticality to reduce bottlenecks in distributed uniprocessors. HPCA 2011: 431-442 - [c52]Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron:
Energy-efficient mechanisms for managing thread context in throughput processors. ISCA 2011: 235-246 - [c51]Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu:
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees. ISCA 2011: 401-412 - [c50]Jeffrey R. Diamond, Martin Burtscher, John D. McCalpin, Byoung-Do Kim, Stephen W. Keckler, James C. Browne:
Evaluation and optimization of multicore performance bottlenecks in supercomputing applications. ISPASS 2011: 32-43 - [c49]Mark Gebhart, Stephen W. Keckler, William J. Dally:
A compile-time managed multi-level register file hierarchy. MICRO 2011: 465-476 - 2010
- [c48]Boris Grot, Stephen W. Keckler, Onur Mutlu:
Topology-Aware Quality-of-Service Support in Highly Integrated Chip Multiprocessors. ISCA Workshops 2010: 357-375 - [c47]Joel Hestness, Boris Grot, Stephen W. Keckler:
Netrace: dependency-driven trace-based network-on-chip simulation. NoCArc@MICRO 2010: 31-36
2000 – 2009
- 2009
- [c46]Mark Gebhart, Bertrand A. Maher, Katherine E. Coons, Jeffrey R. Diamond, Paul Gratz, Mario Marino, Nitya Ranganathan, Behnam Robatmili, Aaron Smith, James H. Burrill, Stephen W. Keckler, Doug Burger, Kathryn S. McKinley:
An evaluation of the TRIPS computer system. ASPLOS 2009: 1-12 - [c45]Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu:
Express Cube Topologies for on-Chip Interconnects. HPCA 2009: 163-174 - [c44]Madhu Saravana Sibi Govindan, Stephen W. Keckler, Doug Burger:
End-to-end validation of architectural power models. ISLPED 2009: 383-388 - [c43]Nitya Ranganathan, Doug Burger, Stephen W. Keckler:
Analysis of the TRIPS prototype block predictor. ISPASS 2009: 195-206 - [c42]Kyle C. Hale, Boris Grot, Stephen W. Keckler:
Segment gating for static energy reduction in Networks-on-Chip. NoCArc@MICRO 2009: 57-62 - [c41]Boris Grot, Stephen W. Keckler, Onur Mutlu:
Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip. MICRO 2009: 268-279 - [e1]Stephen W. Keckler, Luiz André Barroso:
36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA. ACM 2009, ISBN 978-1-60558-526-0 [contents] - 2008
- [j15]Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger:
Multitasking workload scheduling on flexible core chip multiprocessors. SIGARCH Computer Architecture News 36(2): 46-55 (2008) - [c40]Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger:
Multitasking workload scheduling on flexible-core chip multiprocessors. PACT 2008: 187-196 - [c39]Paul Gratz, Boris Grot, Stephen W. Keckler:
Regional congestion awareness for load balance in networks-on-chip. HPCA 2008: 203-214 - [c38]Franziska Roesner, Doug Burger, Stephen W. Keckler:
Counting Dependence Predictors. ISCA 2008: 215-226 - [c37]Jeffrey R. Diamond, Behnam Robatmili, Stephen W. Keckler, Robert A. van de Geijn, Kazushige Goto, Doug Burger:
High performance dense linear algebra on a spatially distributed processor. PPOPP 2008: 63-72 - 2007
- [j14]Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger:
On-Chip Interconnection Networks of the TRIPS Chip. IEEE Micro 27(5): 41-50 (2007) - [j13]John D. Owens, William J. Dally, Ron Ho, D. N. Jayasimha, Stephen W. Keckler, Li-Shiuan Peh:
Research Challenges for On-Chip Interconnection Networks. IEEE Micro 27(5): 96-108 (2007) - [j12]Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang, Doug Burger, Stephen W. Keckler:
A NUCA Substrate for Flexible CMP Cache Sharing. IEEE Trans. Parallel Distrib. Syst. 18(8): 1028-1040 (2007) - [c36]Michael T. Clark, Peter Hofstee, Edward J. Barragy, Ian Buck, Stephen W. Keckler:
The future of multi-core technologies. CLUSTER 2007 - [c35]Heather Hanson, Stephen W. Keckler, Karthick Rajamani, Soraya Ghiasi, Freeman L. Rawson III, Juan Rubio:
Power, Performance, and Thermal Management for High-Performance Systems. IPDPS 2007: 1-8 - [c34]Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler:
Late-binding: enabling unordered load-store queues. ISCA 2007: 347-357 - [c33]Heather Hanson, Stephen W. Keckler, Soraya Ghiasi, Karthick Rajamani, Freeman L. Rawson III, Juan Rubio:
Thermal response to DVFS: analysis with an Intel Pentium M. ISLPED 2007: 219-224 - [c32]Changkyu Kim, Simha Sethumadhavan, M. S. Govindan, Nitya Ranganathan, Divya Gulati, Doug Burger, Stephen W. Keckler:
Composable Lightweight Processors. MICRO 2007: 381-394 - [c31]Paul Gratz, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Robert G. McDonald, Stephen W. Keckler, Doug Burger:
Implementation and Evaluation of a Dynamically Routed Processor Operand Network. NOCS 2007: 7-17 - [c30]Jayaram Mudigonda, Harrick M. Vin, Stephen W. Keckler:
Reconciling performance and programmability in networking systems. SIGCOMM 2007: 73-84 - 2006
- [c29]Simha Sethumadhavan, Robert G. McDonald, Rajagopalan Desikan, Doug Burger, Stephen W. Keckler:
Design and Implementation of the TRIPS Primary Memory System. ICCD 2006: 470-476 - [c28]Paul Gratz, Changkyu Kim, Robert G. McDonald, Stephen W. Keckler, Doug Burger:
Implementation and Evaluation of On-Chip Network Architectures. ICCD 2006: 477-484 - [c27]Ramadass Nagarajan, Xia Chen, Robert G. McDonald, Doug Burger, Stephen W. Keckler:
Critical path analysis of the TRIPS architecture. ISPASS 2006: 37-47 - [c26]Kartik K. Agaram, Stephen W. Keckler, Calvin Lin, Kathryn S. McKinley:
Decomposing memory performance: data structures and phases. ISMM 2006: 95-103 - [c25]Aaron Smith, Ramadass Nagarajan, Karthikeyan Sankaralingam, Robert G. McDonald, Doug Burger, Stephen W. Keckler, Kathryn S. McKinley:
Dataflow Predication. MICRO 2006: 89-102 - [c24]Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger:
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor. MICRO 2006: 480-491 - 2005
- [c23]Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang, Doug Burger, Stephen W. Keckler:
A NUCA substrate for flexible CMP cache sharing. ICS 2005: 31-40 - 2004
- [j11]Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, Michael Dahlin, Lizy Kurian John, Calvin Lin, Charles R. Moore, James H. Burrill, Robert G. McDonald, William Yode:
Scaling to the End of Silicon with EDGE Architectures. IEEE Computer 37(7): 44-55 (2004) - [j10]Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler:
Scalable Hardware Memory Disambiguation for High-ILP Processors. IEEE Micro 24(6): 118-127 (2004) - [j9]Doug Burger, Todd M. Austin, Stephen W. Keckler:
Recent extensions to the SimpleScalar tool suite. SIGMETRICS Performance Evaluation Review 31(4): 4-7 (2004) - [j8]Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore:
TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP. TACO 1(1): 62-93 (2004) - [c22]Ramadass Nagarajan, Sundeep K. Kushwaha, Doug Burger, Kathryn S. McKinley, Calvin Lin, Stephen W. Keckler:
Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures. IEEE PACT 2004: 74-84 - [c21]Rajagopalan Desikan, Simha Sethumadhavan, Doug Burger, Stephen W. Keckler:
Scalable selective re-execution for EDGE architectures. ASPLOS 2004: 120-132 - 2003
- [j7]Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore:
Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture. IEEE Micro 23(6): 46-51 (2003) - [j6]Changkyu Kim, Doug Burger, Stephen W. Keckler:
Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches. IEEE Micro 23(6): 99-107 (2003) - [j5]Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger:
Static energy reduction techniques for microprocessor caches. IEEE Trans. VLSI Syst. 11(3): 303-313 (2003) - [c20]Karthikeyan Sankaralingam, Vincent Ajay Singh, Stephen W. Keckler, Doug Burger:
Routed Inter-ALU Networks for ILP Scalability and Performance. ICCD 2003: 170- - [c19]Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger:
Exploiting Microarchitectural Redundancy For Defect Tolerance. ICCD 2003: 481-488 - [c18]Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore:
Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture. ISCA 2003: 422-433 - [c17]Karthik Natarajan, Heather Hanson, Stephen W. Keckler, Charles R. Moore, Doug Burger:
Microprocessor pipeline energy analysis. ISLPED 2003: 282-287 - [c16]Karthikeyan Sankaralingam, Stephen W. Keckler, William R. Mark, Doug Burger:
Universal Mechanisms for Data-Parallel Architectures. MICRO 2003: 303-314 - [c15]Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler:
Scalable Hardware Memory Disambiguation for High ILP Processors. MICRO 2003: 399-410 - 2002
- [j4]Rajagopalan Desikan, Doug Burger, Stephen W. Keckler, José-Lorenzo Cruz, Fernando Latorre, Antonio González, Mateo Valero:
Errata on "Measuring Experimental Error in Microprocessor Simulation". SIGARCH Computer Architecture News 30(1): 2-4 (2002) - [c14]Changkyu Kim, Doug Burger, Stephen W. Keckler:
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches. ASPLOS 2002: 211-222 - [c13]Premkishore Shivakumar, Michael Kistler, Stephen W. Keckler, Doug Burger, Lorenzo Alvisi:
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic. DSN 2002: 389-398 - [c12]M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas:
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. ISCA 2002: 14-24 - 2001
- [c11]Jaehyuk Huh, Doug Burger, Stephen W. Keckler:
Exploring the Design Space of Future CMPs. IEEE PACT 2001: 199-210 - [c10]Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger:
Static Energy Reduction Techniques for Microprocessor Caches. ICCD 2001: 276-283 - [c9]Ramadass Nagarajan, Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler:
A design space evaluation of grid processor architectures. MICRO 2001: 40-51 - 2000
- [c8]Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckler, Doug Burger:
Clock rate versus IPC: the end of the road for conventional microarchitectures. ISCA 2000: 248-259 - [c7]Nicholas P. Carter, William J. Dally, Whay Sing Lee, Stephen W. Keckler, Andrew Chang:
Processor Mechanisms for Software Shared Memory. ISHPC 2000: 120-133 - [c6]Daniel A. Jiménez, Stephen W. Keckler, Calvin Lin:
The impact of delay on the design of branch predictors. MICRO 2000: 67-76
1990 – 1999
- 1999
- [j3]Stephen W. Keckler, Andrew Chang, Whay Sing Lee, Sandeep Chatterjee, William J. Dally:
Concurrent Event Handling through Multithreading. IEEE Trans. Computers 48(9): 903-916 (1999) - 1998
- [b1]Stephen W. Keckler:
Fast thread communication and synchronization mechanisms for a scalable single chip multiprocessor. Massachusetts Institute of Technology, Cambridge, MA, USA 1998 - [j2]Whay Sing Lee, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Andrew Chang:
An Efficient, Protected Message Interface. IEEE Computer 31(11): 69-75 (1998) - [c5]Andrew Chang, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Whay Sing Lee:
The effects of explicitly parallel mechanisms on the multi-ALU processor cluster pipeline. ICCD 1998: 474-481 - [c4]Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay Sing Lee:
Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor. ISCA 1998: 306-317 - 1997
- [j1]Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay Sing Lee:
The M-machine multicomputer. International Journal of Parallel Programming 25(3): 183-212 (1997) - 1995
- [c3]Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay Sing Lee:
The M-Machine multicomputer. MICRO 1995: 146-156 - 1994
- [c2]Nicholas P. Carter, Stephen W. Keckler, William J. Dally:
Hardware Support for Fast Capability-based Addressing. ASPLOS 1994: 319-327 - 1992
- [c1]Stephen W. Keckler, William J. Dally:
Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism. ISCA 1992: 202-213
Coauthor Index