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2010 – today
- 2017
[j19]Fotis Vartziotis, Xrysovalantis Kavousianos, Panagiotis Georgiou, Krishnendu Chakrabarty:
A Branch-&-Bound Test-Access-Mechanism Optimization Method for Multi-Vdd SoCs. IEEE Trans. on CAD of Integrated Circuits and Systems 36(11): 1911-1924 (2017)- [c43]Fotios Vartziotis, Xrysovalantis Kavousianos:
Critical path - Oriented & thermal aware X-filling for high un-modeled defect coverage. DATE 2017: 642-645 - 2016
- [c42]Panagiotis Georgiou, Fotios Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty:
Two-dimensional time-division multiplexing for 3D-SoCs. ETS 2016: 1-6 - 2015
- [j18]Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji:
Time-Division Multiplexing for Testing DVFS-Based SoCs. IEEE Trans. on CAD of Integrated Circuits and Systems 34(4): 668-681 (2015) - [c41]Fotios Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty:
A branch-&-bound algorithm for TAM optimization in multi-Vdd SoCs. ETS 2015: 1-2 - [c40]Fotios Vartziotis, Xrysovalantis Kavousianos, Panagiotis Georgiou, Krishnendu Chakrabarty:
Test-access-mechanism optimization for multi-Vdd SoCs. ITC 2015: 1-10 - 2014
- [j17]Stefanos Valadimas, Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Xrysovalantis Kavousianos:
The Time Dilation Technique for Timing Error Tolerance. IEEE Trans. Computers 63(5): 1277-1286 (2014) - [j16]Ran Wang, Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty:
Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches. IEEE Trans. on CAD of Integrated Circuits and Systems 33(8): 1231-1244 (2014) - [j15]Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas:
Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches. IEEE Trans. VLSI Syst. 22(1): 13-26 (2014) - [c39]Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Rubin A. Parekhji, Arvind Jain:
Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing. DATE 2014: 1-6 - [c38]Xrysovalantis Kavousianos, Krishnendu Chakrabarty:
Recent advances in single- and multi-site test optimization for DVS-based SoCs. DTIS 2014: 1-6 - 2013
- [j14]Vasileios Tenentes, Xrysovalantis Kavousianos:
High-Quality Statistical Test Compression With Narrow ATE Interface. IEEE Trans. on CAD of Integrated Circuits and Systems 32(9): 1369-1382 (2013) - [c37]Xrysovalantis Kavousianos, Krishnendu Chakrabarty:
Testing for SoCs with advanced static and dynamic power-management capabilities. DATE 2013: 737-742 - 2012
- [j13]Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji:
Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands. IEEE Trans. on CAD of Integrated Circuits and Systems 31(11): 1754-1766 (2012) - [c36]Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji:
Time-division multiplexing for testing SoCs with DVS and multiple voltage islands. European Test Symposium 2012: 1-6 - 2011
- [j12]Xrysovalantis Kavousianos, Krishnendu Chakrabarty:
Generation of Compact Stuck-At Test Sets Targeting Unmodeled Defects. IEEE Trans. on CAD of Integrated Circuits and Systems 30(5): 787-791 (2011) - [j11]Xrysovalantis Kavousianos, Vasileios Tenentes, Krishnendu Chakrabarty, Emmanouil Kalligeros:
Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets. IEEE Trans. VLSI Syst. 19(12): 2330-2335 (2011) - [c35]Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji:
Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands. Asian Test Symposium 2011: 33-39 - [c34]Vasileios Tenentes, Xrysovalantis Kavousianos:
Low Power Test-Compression for High Test-Quality and Low Test-Data Volume. Asian Test Symposium 2011: 46-53 - [c33]Zhaobo Zhang, Xrysovalantis Kavousianos, Yan Luo, Yiorgos Tsiatouhas, Krishnendu Chakrabarty:
Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches. European Test Symposium 2011: 13-18 - [c32]Vasileios Tenentes, Xrysovalantis Kavousianos:
Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs. ICCAD 2011: 747-754 - [c31]Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty:
A BIST scheme for testing and repair of multi-mode power switches. IOLTS 2011: 115-120 - [c30]Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas:
A Robust and Reconfigurable Multi-mode Power Gating Architecture. VLSI Design 2011: 280-285 - 2010
- [j10]Vasileios Tenentes, Xrysovalantis Kavousianos, Emmanouil Kalligeros:
Single and Variable-State-Skip LFSRs: Bridging the Gap Between Test Data Compression and Test Set Embedding for IP Cores. IEEE Trans. on CAD of Integrated Circuits and Systems 29(10): 1640-1644 (2010) - [c29]Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Emmanouil Kalligeros, Vasileios Tenentes:
Defect Coverage-Driven Window-Based Test Compression. Asian Test Symposium 2010: 141-146 - [c28]S. Balatsouka, Vasileios Tenentes, Xrysovalantis Kavousianos, Krishnendu Chakrabarty:
Defect aware X-filling for low-power scan testing. DATE 2010: 873-878 - [c27]Vasileios Tenentes, Xrysovalantis Kavousianos:
Self-Freeze Linear Decompressors for Low Power Testing. ISVLSI 2010: 63-68 - [c26]Vasileios Tenentes, Xrysovalantis Kavousianos:
Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing. ISVLSI (Selected papers) 2010: 217-230
2000 – 2009
- 2009
- [j9]Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
Efficient partial scan cell gating for low-power scan-based testing. ACM Trans. Design Autom. Electr. Syst. 14(2): 28:1-28:15 (2009) - [c25]Xrysovalantis Kavousianos, Krishnendu Chakrabarty:
Generation of compact test sets with high defect coverage. DATE 2009: 1130-1135 - [c24]M. Koutsoupia, Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos:
LFSR-based test-data compression with self-stoppable seeds. DATE 2009: 1482-1487 - 2008
- [j8]Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos:
Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1333-1338 (2008) - [j7]Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos:
Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains. IEEE Trans. VLSI Syst. 16(7): 926-931 (2008) - [c23]Vasileios Tenentes, Xrysovalantis Kavousianos, Emmanouil Kalligeros:
State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores. DATE 2008: 474-479 - [c22]Andreas Floros, Yiorgos Tsiatouhas, Xrysovalantis Kavousianos:
Timing Error Detection and Correction by Time Dilation. VLSI-SoC (Selected Papers) 2008: 271-285 - 2007
- [j6]Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos:
Optimal Selective Huffman Coding for Test-Data Compression. IEEE Trans. Computers 56(8): 1146-1152 (2007) - [j5]Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos:
Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores. IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1070-1083 (2007) - 2006
- [c21]Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos:
Efficient test-data compression for IP cores using multilevel Huffman coding. DATE 2006: 1033-1038 - [c20]Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos:
Efficient Multiphase Test Set Embedding for Scan-based Testing. ISQED 2006: 433-438 - 2005
- [c19]George Gekas, Dimitris Nikolos, Emmanouil Kalligeros, Xrysovalantis Kavousianos:
Power aware test-data compression for scan-based testing. ICECS 2005: 1-4 - [c18]Emmanouil Kalligeros, D. Kaseridis, Xrysovalantis Kavousianos, Dimitris Nikolos:
Reseeding-Based Test Set Embedding with Reduced Test Sequences. ISQED 2005: 226-231 - 2004
- [j4]Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos:
Multiphase BIST: a new reseeding technique for high test-data compression. IEEE Trans. on CAD of Integrated Circuits and Systems 23(10): 1429-1446 (2004) - [c17]Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos, Xrysovalantis Kavousianos:
Low Power Testing by Test Vector Ordering with Vector Repetition. ISQED 2004: 205-210 - [c16]Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos:
An Efficient Test Vector Ordering Method for Low Power Testing. ISVLSI 2004: 285-288 - 2003
- [c15]Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos:
A highly regular multi-phase reseeding technique for scan-based BIST. ACM Great Lakes Symposium on VLSI 2003: 295-298 - [c14]Giorgos Dimitrakopoulos, Xrysovalantis Kavousianos, Dimitris Nikolos:
Virtual-scan: a novel approach for software-based self-testing of microprocessors. ISCAS (5) 2003: 237-240 - [c13]Maciej Bellos, Xrysovalantis Kavousianos, Dimitris Nikolos, Dimitri Kagaris:
DV-TSE: Difference Vector Based Test Set Embedding. VLSI-SOC 2003: 343- - 2002
- [j3]Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST. J. Electronic Testing 18(3): 315-332 (2002) - [j2]Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas:
A new built-in TPG method for circuits with random patternresistant faults. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 859-866 (2002) - [c12]Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos:
A ROMless LFSR Reseeding Scheme for Scan-based BIST. Asian Test Symposium 2002: 206- - [c11]Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST. ISQED 2002: 261-266 - 2001
- [c10]Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
A novel reseeding technique for accumulator-based test pattern generation. ACM Great Lakes Symposium on VLSI 2001: 7-12 - [c9]Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
A New Reseeding Technique for LFSR-Based Test Pattern Generation. IOLTW 2001: 80-86 - [c8]Stanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos:
On the Design of Self-Testing Checkers for Modified Berger Codes. IOLTW 2001: 153-157 - [c7]Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos:
On Accumulator-Based Bit-Serial Test Response Compaction Schemes. ISQED 2001: 350-355 - 2000
- [c6]Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register. ITC 2000: 804-811
1990 – 1999
- 1999
- [j1]Xrysovalantis Kavousianos, Dimitris Nikolos, G. Foukarakis, T. Gnardellis:
New efficient totally self-checking Berger code checkers. Integration 28(1): 101-118 (1999) - [c5]Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou:
Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. DFT 1999: 121-129 - [c4]Xrysovalantis Kavousianos, Dimitris Nikolos:
Modular TSC Checkers for Bose-Lin and Bose Codes. VTS 1999: 354-360 - 1998
- [c3]Xrysovalantis Kavousianos, Dimitris Nikolos:
Novel Single and Double Output TSC Berger Code Checkers. VTS 1998: 348-353 - 1997
- [c2]Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos:
Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes. DFT 1997: 128-136 - [c1]Xrysovalantis Kavousianos, Dimitris Nikolos:
Self-exercising self testing k-order comparators. VTS 1997: 216-221
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last updated on 2018-01-30 22:31 CET by the dblp team