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Rohit Kapur
2010 – today
- 2013
[c46]Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur: An ATE assisted DFD technique for volume diagnosis of scan chains. DAC 2013: 31- 2012
- [c45]Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur: A Diagnosability Metric for Test Set Selection Targeting Better Fault Detection. VLSI Design 2012: 436-441
- 2011
- [c44]Uzair Shah Syed, Krishnendu Chakrabarty, Anshuman Chandra, Rohit Kapur: 3D-Scalable Adaptive Scan (3D-SAS). 3DIC 2011: 1-6
- [c43]Jyotirmoy Saikia, Pramod Notiyath, Santosh Kulkarni, Ashok Anbalan, Rajesh Uppuluri, Tammy Fernandes, Parthajit Bhattacharya, Rohit Kapur: Predicting Scan Compression IP Configurations for Better QoR. Asian Test Symposium 2011: 261-266
- [c42]Anshuman Chandra, Jyotirmoy Saikia, Rohit Kapur: Breaking the Test Application Time Barriers in Compression: Adaptive Scan-Cyclical (AS-C). Asian Test Symposium 2011: 432-437
- [c41]Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur: Multiple Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization. VLSI Design 2011: 364-369
- [c40]Xiaoqing Wen, Mohammad Tehranipoor, Rohit Kapur, Anand Bhat, Amitava Majumdar, LeRoy Winemberg: Special session 5B: Panel How much toggle activity should we be testing with? VTS 2011: 114
- 2010
- [j16]
- [j15]
- [j14]
2000 – 2009
- 2009
- [j13]Rohit Kapur, Paul Reuter, Sandeep Bhatia, Brion L. Keller: CTL and Its Usage in the EDA Industry. IEEE Design & Test of Computers 26(1): 36-43 (2009)
- [c39]
- [c38]Anshuman Chandra, Yasunari Kanzawa, Rohit Kapur: Proactive management of X's in scan chains for compression. ISQED 2009: 260-265
- 2008
- [j12]Rohit Kapur, Subhasish Mitra, Thomas W. Williams: Historical Perspective on Scan Compression. IEEE Design & Test of Computers 25(2): 114-120 (2008)
- [c37]Anshuman Chandra, Felix Ng, Rohit Kapur: Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction. DATE 2008: 462-467
- [c36]Anshuman Chandra, Rohit Kapur: Interval Based X-Masking for Scan Compression Architectures. ISQED 2008: 821-826
- [c35]Anshuman Chandra, Rohit Kapur: Bounded Adjacent Fill for Low Capture Power Scan Testing. VTS 2008: 131-138
- 2007
- [j11]Rohit Kapur, T. Finklea, Felix Ng, Anshuman Chandra, Sanjay Ramnath, Peter Wohl, Thomas W. Williams, Ashok Anbalan, Sandeep S. Kulkarni, Tammy Fernandes, Pramod Notiyath, Rajesh Uppuluri: DFT MAX and Power. J. Low Power Electronics 3(2): 199-205 (2007)
- [c34]
- [c33]Maria Gkatziani, Rohit Kapur, Qing Su, Ben Mathew, Roberto Mattiuzzo, Laura Tarantini, Cy Hay, Salvatore Talluto, Thomas W. Williams: Accurately Determining Bridging Defects from Layout. DDECS 2007: 87-90
- [c32]Rohit Kapur, Jindrich Zejda, Thomas W. Williams: Fundamentals of timing information for test: How simple can we get? ITC 2007: 1-7
- [c31]Peter Wohl, John A. Waicukauski, Rohit Kapur, Sanjay Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini: Minimizing the Impact of Scan Compression. VTS 2007: 67-74
- [c30]Anshuman Chandra, Haihua Yan, Rohit Kapur: Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction. VTS 2007: 84-92
- 2006
- [c29]Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie: OCI: Open Compression Interface. ITC 2006: 1-4
- 2005
- [c28]
- [c27]Peter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur: Efficient compression of deterministic patterns into multiple PRPG seeds. ITC 2005: 10
- 2004
- [c26]
- [c25]Nodari Sitchinava, Samitha Samaranayake, Rohit Kapur, Emil Gizdarski, Frederic Neuveux, Thomas W. Williams: Changing the Scan Enable during Shift. VTS 2004: 73-78
- 2003
- [j10]Bruce Cory, Rohit Kapur, Bill Underwood: Speed Binning with Path Delay Test in 150-nm Technology. IEEE Design & Test of Computers 20(5): 41-45 (2003)
- [c24]Nahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch: Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture. DATE 2003: 10110-10115
- [c23]Francisco DaSilva, Yervant Zorian, Lee Whetsel, Karim Arabi, Rohit Kapur: Overview of the IEEE P1500 Standard. ITC 2003: 988-997
- [c22]Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams: A Reconfigurable Shared Scan-in Architecture. VTS 2003: 9-14
- 2002
- [j9]Samitha Samaranayake, Nodari Sitchinava, Rohit Kapur, Minesh B. Amin, Thomas W. Williams: Dynamic Scan: Driving Down the Cost of Test. IEEE Computer 35(10): 63-68 (2002)
- [j8]Erik Jan Marinissen, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti, Yervant Zorian: On IEEE P1500's Standard for Embedded Core Test. J. Electronic Testing 18(4-5): 365-383 (2002)
- [c21]
- [c20]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams: Enhancing test efficiency for delay fault testing using multiple-clocked schemes. DAC 2002: 371-374
- [c19]Rohit Kapur, Thomas W. Williams, M. Ray Mercer: Directed-Binary Search in Logic BIST Diagnostics. DATE 2002: 1121
- [c18]Nahmsuk Oh, Rohit Kapur, Thomas W. Williams: Fast seed computation for reseeding shift register in test pattern compression. ICCAD 2002: 76-81
- [c17]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams: Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. ITC 2002: 407-416
- [c16]Loïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur: Integrating DFT in the Physical Synthesis Flow. ITC 2002: 788-795
- 2001
- [j7]Rohit Kapur, R. Chandramouli, Thomas W. Williams: Strategies for Low-Cost Test. IEEE Design & Test of Computers 18(6): 47-54 (2001)
- [c15]Rohit Kapur, Maurice Lousberg, Tony Taylor, Brion L. Keller, Paul Reuter, Douglas Kay: CTL the language for describing core-based test. ITC 2001: 131-139
- [c14]
- [c13]Ajay Khoche, Rohit Kapur, David Armstrong, Thomas W. Williams, Mick Tegethoff, Jochen Rivoir: A new methodology for improved tester utilization. ITC 2001: 916-923
- [c12]Dwayne Burek, Garen Darbinyan, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti: IP and Automation to Support IEEE P1500. VTS 2001: 411-412
- 2000
- [j6]Rohit Kapur, Cy Hay, Thomas W. Williams: The Mutating Metric for Benchmarking Test. IEEE Design & Test of Computers 17(3): 18-21 (2000)
- [c11]
- [c10]Thomas W. Williams, Rohit Kapur: Design for Testability in Nanometer Technologies; Searching for Quality. ISQED 2000: 167-172
- [c9]Yervant Zorian, Erik Jan Marinissen, Rohit Kapur: On using IEEE P1500 SECT for test plug-n-play. ITC 2000: 770-777
1990 – 1999
- 1999
- [j5]Rohit Kapur, Thomas W. Williams: Tough Challenges as Design and Test Go Nanometer - Guest Editors' Introduction. IEEE Computer 32(11): 42-45 (1999)
- [c8]Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel: Towards a standard for embedded core test: an example. ITC 1999: 616-627
- [c7]
- 1997
- [j4]Magdy S. Abadir, Rohit Kapur: Cost-Driven Ranking of Memory Elements for Partial Intrusion. IEEE Design & Test of Computers 14(3): 45-50 (1997)
- 1996
- [j3]Rohit Kapur, Edward F. Miller: System Test and Reliability: Techniques for Avoiding Failure (Guest Editors' Introduction). IEEE Computer 29(11): 28-30 (1996)
- [j2]Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams: A weighted random pattern test generation system. IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 1020-1025 (1996)
- [c6]Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly: IDDQ Test: Sensitivity Analysis of Scaling. ITC 1996: 786-792
- 1994
- [c5]Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams: Design of an Efficient Weighted-Random-Pattern Generation System. ITC 1994: 491-500
- [c4]Jaehong Park, Mark Naivar, Rohit Kapur, M. Ray Mercer, Thomas W. Williams: Limitations in predicting defect level based on stuck-at fault coverage. VTS 1994: 186-191
- 1992
- [j1]Rohit Kapur, M. Ray Mercer: Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes. IEEE Trans. Computers 41(12): 1580-1588 (1992)
- [c3]M. Ray Mercer, Rohit Kapur, Don E. Ross: Functional Approaches to Generating Orderings for Efficient Symbolic Representations. DAC 1992: 624-627
- [c2]Rohit Kapur, Jaehong Park, M. Ray Mercer: All Tests for a Fault Are Not Equally Valuable for Defect Detection. ITC 1992: 762-769
- 1991
- [c1]Kenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer: Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams. DAC 1991: 417-420
Coauthor Index
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last updated on 2013-05-29 01:53 CEST by the dblp team