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 | 2013 | |
|---|---|---|
| j24 |      | S. Srinivasan, V. Kamakoti, A. Bhattacharya: A Novel Algorithm for Fast Synthesis of DNA Probes on Microarrays. JETC 9(1): 1 (2013) |
| 2012 | ||
| j23 | | Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli: A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands. J. Electrical and Computer Engineering 2012 (2012) |
| j22 | | Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti: Interconnect Aware Test Power Reduction. J. Low Power Electronics 8(4): 516-525 (2012) |
| j21 | | Rama Kumar Pasumarthi, V. R. Devanathan, V. Visvanathan, Seetal Potluri, V. Kamakoti: Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs. J. Low Power Electronics 8(5): 684-695 (2012) |
| 2011 | ||
| j20 | | Shoaib Mohammed, S. K. Noor Mahammad, V. Kamakoti: Hardware based genetic evolution of self-adaptive arbitrary response FIR filters. Appl. Soft Comput. 11(1): 842-854 (2011) |
| j19 | | Karthik Raghavan, V. Kamakoti: ROSY: recovering processor and memory systems from hard errors. Operating Systems Review 45(3): 82-84 (2011) |
| c50 | | Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli: A Simulation Based Buffer Sizing Algorithm for Network on Chips. ISVLSI 2011: 206-211 |
| c49 | | Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti: Post-Synthesis Circuit Techniques for Runtime Leakage Reduction. ISVLSI 2011: 319-320 |
| 2010 | ||
| j18 | | Kavish Seth, V. Kamakoti, S. Srinivasan: Efficient Motion Vector Recovery Algorithm for H.264 Using B-Spline Approximation. TBC 56(4): 467-480 (2010) |
| c48 | | Lavanya Jagan, Camelia Hora, Bram Kruseman, Stefan Eichenberger, Ananta K. Majhi, V. Kamakoti: Impact of Temperature on Test Quality. VLSI Design 2010: 276-281 |
| 2009 | ||
| j17 | | George Kurian, Narayana Rao, Virendra Patidar, V. Kamakoti, Srivaths Ravi: Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures. J. Low Power Electronics 5(1): 58-68 (2009) |
| j16 | | K. Shyamala, J. Vimalkumar, V. Kamakoti: Novel SAT-Based Peak Dynamic Power Estimation for Digital Circuits. J. Low Power Electronics 5(4): 429-438 (2009) |
| j15 | | K. Kunal, K. George, M. Gautam, V. Kamakoti: HTM design spaces: complete decoupling from caches and achieving highly concurrent transactions. Operating Systems Review 43(2): 98-99 (2009) |
| c47 | | Lavanya Jagan, Ratan Deep Singh, V. Kamakoti, Ananta K. Majhi: Efficient Grouping of Fail Chips for Volume Yield Diagnostics. VLSI Design 2009: 97-102 |
| 2008 | ||
| j14 | | V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti: A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. J. Low Power Electronics 4(1): 101-110 (2008) |
| j13 | | Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti, Vivekananda M. Vedula, K. S. Maneperambil: Automatic Constraint Based Test Generation for Behavioral HDL Models. IEEE Trans. VLSI Syst. 16(4): 408-421 (2008) |
| 2007 | ||
| j12 | | Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti: A novel approach to the placement and routing problems for field programmable gate arrays. Appl. Soft Comput. 7(1): 455-470 (2007) |
| j11 | | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti: Variation-Tolerant, Power-Safe Pattern Generation. IEEE Design & Test of Computers 24(4): 374-384 (2007) |
| j10 | | K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula: Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits. J. Low Power Electronics 3(3): 280-292 (2007) |
| j9 | | A. Pavan Kumar, V. Kamakoti, Sukhendu Das: System-on-programmable-chip implementation for on-line face recognition. Pattern Recognition Letters 28(3): 342-349 (2007) |
| c46 | | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti: Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. DATE 2007: 534-539 |
| c45 | | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti: A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test. ITC 2007: 1-10 |
| c44 | | V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti: PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. ITC 2007: 1-9 |
| c43 | | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti: Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. VLSI Design 2007: 351-356 |
| c42 | | K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula: Controllability-driven Power Virus Generation for Digital Circuits. VLSI Design 2007: 407-412 |
| c41 | | K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula: Power Virus Generation Using Behavioral Models of Circuits. VTS 2007: 35-42 |
| c40 | | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti: Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. VTS 2007: 167-172 |
| i1 | | Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti: FPGA based Agile Algorithm-On-Demand Co-Processor. CoRR abs/0710.4824 (2007) |
| 2006 | ||
| j8 | | K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam: Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. J. Low Power Electronics 2(3): 425-436 (2006) |
| j7 | | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti: On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. J. Low Power Electronics 2(3): 464-476 (2006) |
| c39 | | K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam: Delay and peak power minimization for on-chip buses using temporal redundancy. ACM Great Lakes Symposium on VLSI 2006: 119-122 |
| c38 | | Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti: An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. VLSI Design 2006: 507-510 |
| c37 | | Kavish Seth, K. N. Viswajith, S. Srinivasan, V. Kamakoti: Ultra Folded High-Speed Architectures for Reed-Solomon Decoders. VLSI Design 2006: 517-520 |
| 2005 | ||
| j6 | | L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti: Pseudo-online testing methodologies for various components of field programmable gate arrays. Microprocessors and Microsystems 29(2-3): 99-119 (2005) |
| c36 | | Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti: A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. ASP-DAC 2005: 791-794 |
| c35 | | Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti: A function generator-based reconfigurable system. ASP-DAC 2005: 905-909 |
| c34 | | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan: Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. ASP-DAC 2005: 1200-1203 |
| c33 | | K. Uday Bhaskar, M. Prasanth, V. Kamakoti, Kailasnath Maneparambil: A Framework for Automatic Assembly Program Generator (A2PG) for Verification and Testing of Processor Cores. Asian Test Symposium 2005: 40-45 |
| c32 | | Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti: FPGA based Agile Algorithm-On-Demand Co-Processor. DATE 2005: 82-83 |
| c31 | | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan: Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). FPGA 2005: 265 |
| c30 | | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan: Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs. IPDPS 2005 |
| c29 | | K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti: A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip. VLSI Design 2005: 207-212 |
| c28 | | R. Manimegalai, E. Siva Soumya, V. Muralidharan, Balaraman Ravindran, V. Kamakoti, D. Bhatia: Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines. VLSI Design 2005: 451-456 |
| c27 | | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan: Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. VLSI Design 2005: 736-741 |
| c26 | | Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti: A Principal Component Neural Network-Based Face Recognition System and Its ASIC Implementation. VLSI Design 2005: 795-798 |
| 2004 | ||
| c25 | | A. Manoj Kumar, Jayaram Bobba, V. Kamakoti: MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis. DATE 2004: 922-929 |
| c24 | | A. Manoj Kumar, B. Jayaram, V. Kamakoti: SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis. FPGA 2004: 251 |
| c23 | | R. Manimegalai, A. Manoj Kumar, B. Jayaram, V. Kamakoti: MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks. FPL 2004: 1185 |
| c22 | | R. Manimegalai, B. Jayaram, A. Manoj Kumar, V. Kamakoti: SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis. FPT 2004: 57-64 |
| c21 | | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Vijaykrishnan Narayanan: A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs. FPT 2004: 121-128 |
| c20 | | Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti: A Hardware-Directed Face Recognition System Based on Local Eigen-analysis with PCNN. ICONIP 2004: 327-332 |
| c19 | | A. Pavan Kumar, Sukhendu Das, V. Kamakoti: Face Recognition Using Weighted Modular Principle Component Analysis. ICONIP 2004: 362-367 |
| c18 |  | A. Pavan Kumar, V. Kamakoti, Sukhendu Das: An Architecture for Real Time Face Recognition Using WMPCA. ICVGIP 2004: 644-649 |
| c17 | | A. Manoj Kumar, B. Jayaram, R. Manimegalai, V. Kamakoti: MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Arrays. IPDPS 2004 |
| c16 | | Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti: An Evolutionary Algorithm for Automatic Spatial Partitioning in Reconfigurable Environments. MICAI 2004: 735-745 |
| c15 | | P. Subrahmanya, R. Manimegalai, V. Kamakoti, Madhu Mutyam: A Bus Encoding Technique for Power and Cross-talk Minimization. VLSI Design 2004: 443-448 |
| c14 | | Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, V. Bala Kuteshwar: A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation. VLSI Design 2004: 1071-1076 |
| 2003 | ||
| c13 | | L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti: A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAs. Asian Test Symposium 2003: 262-267 |
| c12 | | L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti: Testable Clock Routing Architecture for Field Programmable Gate Arrays. FPL 2003: 1044-1047 |
| c11 | | B. Jayaram, A. Manoj Kumar, V. Kamakoti: Parallel Partitioning Techniques for Logic Minimization Using Redundancy Identification. HiPC 2003: 174-183 |
| c10 | | Permandla Pratibha, Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Ganesh, V. Kamakoti: A Parallel Evolutionary Approach to Spatial Partitioning in Reconfigurable Environments. IICAI 2003: 938-951 |
| c9 | | Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti: A Parallel Genetic Approach to the Placement Problem for Field Programmable Gate Arrays. IPDPS 2003: 184 |
| c8 | | M. Madhu, V. Srinivasa Murty, V. Kamakoti: Dynamic Coding Technique For Low-Power Data Bus. ISVLSI 2003: 252-253 |
| c7 | | L. Kalyan Kumar, Aditya S. Ramani, Amol J. Mupid, V. Kamakoti, Sivaprakasam Suresh: On-Line Location of Multiple Faults in LUT Based Reconfigurable Systems. VLSI 2003: 224-232 |
| 2002 | ||
| c6 | | Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti: A novel three phase parallel genetic approach to routing for field programmable gate arrays. FPT 2002: 336-339 |
| 2001 | ||
| c5 | | K. Srinathan, C. Pandu Rangan, V. Kamakoti: Toward Optimal Player Weights in Secure Distributed Protocols. INDOCRYPT 2001: 232-241 |
| 1999 | ||
| j5 | | V. Annamalai, C. S. Krishnamoorthy, V. Kamakoti: Adaptive finite element analysis on a parallel and distributed environment. Parallel Computing 25(12): 1413-1434 (1999) |
| 1998 | ||
| c4 | | Thomas Graf, V. Kamakoti, N. S. Janaki Latha, C. Pandu Rangan: The Colored Sector Search Tree: A Dynamic Data Structure for Efficient High Dimensional Nearest-Foreign-Neighbor Queries. COCOON 1998: 35-44 |
| 1997 | ||
| j4 | | Thomas Graf, V. Kamakoti: Sparse Dominance Queries for Many Points in Optimal Time and Space. Inf. Process. Lett. 64(6): 287-291 (1997) |
| c3 | | V. Kamakoti, N. Balakrishnan: Efficient Algorithms for Prefix and General Prefix Computations on Distributed Shared Memory Systems with Applications. ICPADS 1997: 44-51 |
| 1995 | ||
| j3 | | K. Arvind, V. Kamakoti, C. Pandu Rangan: Efficient Parallel Algorithms for Permutation Graphs. J. Parallel Distrib. Comput. 26(1): 116-124 (1995) |
| j2 | | V. Kamakoti, Kamala Krithivasan, C. Pandu Rangan: An Efficient Randomized Algorithm for the Closest Pair Problem on Colored Point Sets. Nord. J. Comput. 2(1): 28-40 (1995) |
| c2 | | V. Kamakoti, Kamala Krithivasan, C. Pandu Rangan: Efficient Randomized Incremental Algorithm For The Closest Pair Problem Using Leafary Trees. COCOON 1995: 71-80 |
| 1994 | ||
| c1 | | P. Jagan Mohan, V. Kamakoti, C. Pandu Rangan: Efficient Randomized Parallel Algorithm for the Closest Pair Problem in D-dimension. IFIP Congress (1) 1994: 547-552 |
| 1992 | ||
| j1 | | V. Kamakoti, C. Pandu Rangan: An Optimal Algorithm for Reconstructing a Binary Tree. Inf. Process. Lett. 42(2): 113-115 (1992) |
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