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2000 – 2009
- 2008
[j10]Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, Xianlong Hong:
Fashion: A Fast and Accurate Solution to Global Routing Problem. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 726-737 (2008)- 2007
- [c23]Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong:
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. ASP-DAC 2007: 256-261 - [c22]Chunta Chu, Xinyi Zhang, Lei He, Tong Jing:
Temperature aware microprocessor floorplanning considering application dependent power load. ICCAD 2007: 586-589 - [c21]Yu Hu, King Ho Tam, Tong Jing, Lei He:
Fast dual-vdd buffering based on interconnect prediction and sampling. SLIP 2007: 95-102 - 2006
- [j9]Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu:
A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design. Integration 39(4): 457-473 (2006) - [j8]Yu Hu, Tong Jing, Zhe Feng, Xianlong Hong, Xiaodong Hu, Guiying Yan:
ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm. J. Comput. Sci. Technol. 21(1): 147-152 (2006) - [j7]Jingyu Xu, Xianlong Hong, Tong Jing, Yang Yang:
Obstacle-avoiding rectilinear minimum-delay Steiner tree construction toward IP-block-based SOC design. IEEE Trans. on Circuits and Systems 53-II(4): 309-313 (2006) - [c20]Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, Guiying Yan:
DraXRouter: global routing in X-Architecture with dynamic resource assignment. ASP-DAC 2006: 618-623 - [c19]Yiyu Shi, Tong Jing, Lei He, Zhe Feng, Xianlong Hong:
CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model. ASP-DAC 2006: 630-635 - [c18]S. P. Shang, Xiaodong Hu, Tong Jing:
Average lengths of wire routing under M-architecture and X-architecture. ISCAS 2006 - [c17]Zhe Feng, Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan:
An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane. ISPD 2006: 48-55 - 2005
- [j6]Jingyu Xu, Xianlong Hong, Tong Jing:
Timing-Driven Global Routing with Efficient Buffer Insertion. IEICE Transactions 88-A(11): 3188-3195 (2005) - [j5]Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang:
Spanning graph-based nonrectilinear steiner tree algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1066-1075 (2005) - [c16]Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu, Guiying Yan:
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. ASAP 2005: 198-203 - [c15]Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan:
The polygonal contraction heuristic for rectilinear Steiner tree construction. ASP-DAC 2005: 1-6 - [c14]Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan:
An-OARSMan: obstacle-avoiding routing tree construction with good length performance. ASP-DAC 2005: 7-12 - [c13]Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He:
A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem. ASP-DAC 2005: 115-120 - [c12]Songpu Shang, Xiaodong Hu, Tong Jing:
Rotational Steiner Ratio Problem Under Uniform Orientation Metrics. CJCDGCGT 2005: 166-176 - [c11]Jingyu Xu, Xianlong Hong, Tong Jing:
Timing-driven global routing with efficient buffer insertion. ISCAS (3) 2005: 2449-2452 - [c10]Jingyu Xu, Xianlong Hong, Tong Jing, Yang Yang:
Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design. ISQED 2005: 616-621 - [c9]Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan:
A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design. SAMOS 2005: 344-353 - 2004
- [j4]Tong Jing, Xianlong Hong, Jingyu Xu, Haiyun Bao, Chung-Kuan Cheng, Jun Gu:
UTACO: a unified timing and congestion optimization algorithm for standard cell global routing. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 358-365 (2004) - [c8]Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu:
A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design. ASP-DAC 2004: 677-682 - [c7]Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang:
Efficient octilinear Steiner tree construction based on spanning graphs. ASP-DAC 2004: 687-690 - [c6]Ling Zhang, Tong Jing, Xianlong Hong, Jingyu Xu, Jinjun Xiong, Lei He:
Performance and RLC crosstalk driven global routing. ISCAS (5) 2004: 65-68 - [c5]Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan:
An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design. PATMOS 2004: 442-452 - 2003
- [j3]Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu:
An efficient hierarchical timing-driven Steiner tree algorithm for global routing. Integration 35(2): 69-84 (2003) - [j2]Tong Jing, Xianlong Hong, Haiyun Bao, Jingyu Xu, Jun Gu:
SSTT: Efficient Local Search for GSI Global Routing. J. Comput. Sci. Technol. 18(5): 632-640 (2003) - [j1]Xianlong Hong, Tong Jing, Jingyu Xu, Haiyun Bao, Jun Gu:
CNB: A Critical-Network-Based Timing Optimization Method for Standard Cell Global Routing. J. Comput. Sci. Technol. 18(6): 732-738 (2003) - [c4]Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Chung-Kuan Cheng, Jun Gu:
UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing. ASP-DAC 2003: 834-839 - [c3]Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu:
A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design. ASP-DAC 2003: 847-850 - 2002
- [c2]Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Jun Gu:
A novel and efficient timing-driven global router for standard cell layout design based on critical network concept. ISCAS (1) 2002: 165-168 - [c1]Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu:
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. VLSI Design 2002: 473-478
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last updated on 2018-02-15 21:44 CET by the dblp team