Chris R. Jesshope

Mike Lankamp, Raphael 'kena' Poss, Qiang Yang, Jian Fu, M. Irfan Uddin, Chris R. Jesshope: MGSim - Simulation tools for multi-core processor architectures. CoRR abs/1302.1390 (2013)

Raphaël Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Chris R. Jesshope: Apple-CORE: Microgrids of SVP Cores - Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management. DSD 2012: 501-508

M. Irfan Uddin, Michiel W. van Tol, Chris R. Jesshope: High Level Simulation of SVP Many-Core Systems. Parallel Processing Letters 21(4): 413-438 (2011)

Qiang Yang, Chris R. Jesshope, Jian Fu: A Micro Threading Based Concurrency Model for Parallel Computing. IPDPS Workshops 2011: 1668-1674

Michiel W. van Tol, Roy Bakker, Merijn Verstraaten, Clemens Grelck, Chris R. Jesshope: Efficient Memory Copy Operations on the 48-core Intel SCC Processor. MARC Symposium 2011: 13-18

Merijn Verstraaten, Clemens Grelck, Michiel W. van Tol, Roy Bakker, Chris R. Jesshope: Mapping Distributed S-Net on the 48-core Intel SCC processor. MARC Symposium 2011: 41-46

Thomas A. M. Bernard, Clemens Grelck, Chris R. Jesshope: On the Compilation of a Language for General Concurrent Target Architectures. Parallel Processing Letters 20(1): 51-69 (2010)

Thomas A. M. Bernard, Clemens Grelck, Michael A. Hicks, Chris R. Jesshope, Raphaël Poss: Resource-Agnostic Programming for Many-Core Microgrids. Euro-Par Workshops 2010: 109-116

Michael A. Hicks, Michiel W. van Tol, Chris R. Jesshope: Towards scalable I/O on a many-core architecture. ICSAMOS 2010: 341-348

Kostas Bousias, Liang Guang, Chris R. Jesshope, Mike Lankamp: Implementation and evaluation of a microthread architecture. Journal of Systems Architecture - Embedded Systems Design 55(3): 149-161 (2009)

Michiel W. van Tol, Chris R. Jesshope, Mike Lankamp, Simon Polstra: An implementation of the SANE Virtual Processor using POSIX threads. Journal of Systems Architecture - Embedded Systems Design 55(3): 162-169 (2009)

Chris R. Jesshope, Mike Lankamp, Li Zhang: The implementation of an SVP many-core processor and the evaluation of its memory architecture. SIGARCH Computer Architecture News 37(2): 38-45 (2009)

Chris R. Jesshope, Mike Lankamp, Li Zhang: Evaluating CMPs and Their Memory Architecture. ARCS 2009: 246-257

Martti Forsell, Peter Hofstee, Ahmed Jerraya, Chris R. Jesshope, Uzi Vishkin, Jesper Larsson Träff: HPPC 2009 Panel: Are Many-Core Computer Vendors on Track? Euro-Par Workshops 2009: 9-15

Chris R. Jesshope: Operating Systems in silicon and the Dynamic Management of Resources in Many-Core Chips. Parallel Processing Letters 18(2): 257-274 (2008)

Thuy Duong Vu, Li Zhang, Chris R. Jesshope: The Verification of the On-Chip COMA Cache Coherence Protocol. AMAST 2008: 413-429

Chris R. Jesshope: Building a Concurrency and Resource Allocation Model into a Processor's ISA. Euro-Par Workshops 2008: 129-130

Thomas A. M. Bernard, Kostas Bousias, Liang Guang, Chris R. Jesshope, Mike Lankamp, Michiel W. van Tol, Li Zhang: A general model of concurrency and its implementation as many-core dynamic RISC processors. ICSAMOS 2008: 1-9

Chris R. Jesshope: Introduction to Programming Multicores. SAMOS 2008: 207

Chris R. Jesshope, Jean-Marc Philippe, Michiel W. van Tol: An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency. SAMOS 2008: 218-228

Nabil Hasasneh, Ian Bell, Chris R. Jesshope: Asynchronous arbiter for micro-threaded chip multiprocessors. Journal of Systems Architecture 53(5-6): 253-262 (2007)

Nabil Hasasneh, Ian Bell, Chris R. Jesshope: High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids. AICCSA 2007: 301-308

Li Zhang, Chris R. Jesshope: On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores. Euro-Par Workshops 2007: 38-48

Thuy Duong Vu, Chris R. Jesshope: Formalizing SANE Virtual Processor in Thread Algebra. ICFEM 2007: 345-365

Thomas A. M. Bernard, Chris R. Jesshope, Peter M. W. Knijnenburg: Strategies for Compiling µ TC to Novel Chip Multiprocessors. SAMOS 2007: 127-138

Keqiu Li, Chris R. Jesshope, Hai Jin, Jean-Luc Gaudiot (Eds.): Network and Parallel Computing, IFIP International Conference, NPC 2007, Dalian, China, September 18-21, 2007, Proceedings. Lecture Notes in Computer Science 4672, Springer 2007, isbn 978-3-540-74783-3

Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope: Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors. Comput. J. 49(2): 211-233 (2006)

Chris R. Jesshope, Alexander V. Shafarenko: Special issue on Micro-grids - Guest Editor Introduction. International Journal of Parallel Programming 34(3): 189-192 (2006)

Chris R. Jesshope, Alexander V. Shafarenko: Guest Editor's Introduction (Part 2). International Journal of Parallel Programming 34(4): 319-322 (2006)

Ian Bell, Nabil Hasasneh, Chris R. Jesshope: Supporting Microthread Scheduling and Synchronisation in CMPs. International Journal of Parallel Programming 34(4): 343-381 (2006)

Chris R. Jesshope: Microthreading a Model for Distributed Instruction-level Concurrency. Parallel Processing Letters 16(2): 209-228 (2006)

Chris R. Jesshope: muTC - An Intermediate Language for Programming Chip Multiprocessors. Asia-Pacific Computer Systems Architecture Conference 2006: 147-160

Nabil Hasasneh, Ian Bell, Chris R. Jesshope: Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors. ARCS 2006: 252-267

Chris R. Jesshope, Colin Egan (Eds.): Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings. Lecture Notes in Computer Science 4186, Springer 2006, isbn 3-540-40056-7

Kostas Bousias, Chris R. Jesshope: The Challenges of Massive On-Chip Concurrency. Asia-Pacific Computer Systems Architecture Conference 2005: 157-170

Chris R. Jesshope: Microgrids - The exploitation of massive on-chip concurrency. High Performance Computing Workshop 2004: 203-223

Lipeng Wen, Chris R. Jesshope: A General Learning Management System Based on Schema-driven Methodology. ICALT 2004: 0-

Chris R. Jesshope: Scalable Instruction-Level Parallelism.. SAMOS 2004: 383-392

Chris R. Jesshope: Multi-threaded Microprocessors - Evolution or Revolution. Asia-Pacific Computer Systems Architecture Conference 2003: 21-45

Lipeng Wen, Chris R. Jesshope: Web Services Technology and Learning Technology- A Web-Services Model for Constructing Decentralized Virtual Learning Environments. ICWS 2003: 507-514

Chris R. Jesshope: Cost-Effective Multimedia in On-line Teaching. Educational Technology & Society 4(3) (2001)

Chris R. Jesshope: Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines. ACSAC 2001: 80-88

Ramón Beivide, Chris R. Jesshope, Antonio Robles, Cruz Izu: Topic 12: Routing and Communication in Interconnection Networks. Euro-Par 2001: 611-612

Regina Gehne, Chris R. Jesshope, Zhenzi Zhang: Technology Integrated Learning Environment - A Web-based Distance Learning System. IMSA 2001: 1-6

Hong Hong, Neena Albi, Kinshuk, Xiaoqin He, Ashok Patel, Chris R. Jesshope: Adaptivity in Web-based Educational System. WWW Posters 2001

Chris R. Jesshope, Bing Luo: Micro-Threading: A New Approach to Future RISC. ACAC 2000: 34-41

Chris R. Jesshope: Computers as Tutors: Solving the Crisis in Education. Educational Technology & Society 2(4) (1999)

Chris R. Jesshope: Parallel Computer Architecture - What Is Its Future? Introduction. Euro-Par 1999: 695-697

Murray Pearson, Chris R. Jesshope: Multi-campus teaching using computer networks. ACSE 1998: 106-111

Julian A. B. Dines, John F. Snowdon, Marc P. Y. Desmulliez, Dima B. Barsky, Alexander V. Shafarenko, Chris R. Jesshope: Optical Interconnectivity in a Scalable Data-Parallel System. J. Parallel Distrib. Comput. 41(1): 120-130 (1997)

Chris R. Jesshope: Web based teaching: a minimalist approach. ACSE 1997: 16-23

Julian A. B. Dines, John F. Snowdon, Marc P. Y. Desmulliez, D. T. Nielson, Dima B. Barsky, Alexander V. Shafarenko, Chris R. Jesshope: Optical Interconnection hardware for scalable systems. PDPTA 1996: 367-374

Chris R. Jesshope, Vesselin Jossifov, Wolfgang Wilhelmi (Eds.): Parcella 1994, VI. International Workshop on Parallel Processing by Cellular Automata and Arrays, Potsdam, September 21-23, 1994. Proceedings. Mathematical Research 81, Akademie Verlag, Berlin 1994, isbn 3-05-501602-5

Chris R. Jesshope, Cruz Izu: The MP1 Network Chip and its Application to Parallel Computers. Comput. J. 36(8): 763-777 (1993)

Cruz Izu, Ramón Beivide, Chris R. Jesshope, Agustin Arruabarrena: Experimental evaluation of Mad Postman bidimensional routing networks. Microprocessing and Microprogramming 38(1-5): 33-41 (1993)

Chris R. Jesshope: Latency Reduction in VLSI Routers. Parallel Processing Letters 3: 485-494 (1993)

Vladimir Getov, Chris R. Jesshope: Simulation Facility of Distributed Memory System with "Mad Postman" Communication Network. EDMCC 1991: 224-233

Chris R. Jesshope, P. R. Miller, Jay T. Yantchev: High Performance Communications in Processor Networks. ISCA 1989: 150-157

Chris R. Jesshope: Transputers and switches as objects in OCCAM. Parallel Computing 8(1-3): 19-30 (1988)

Chris R. Jesshope, Philip Miller, Jelio Yantchev: Programming with active data. Parcella 1988: 111-129

Chris R. Jesshope, M. J. Crawley, G. L. Lovegrove: An Intelligent Pascal Editor for a Graphical Oriented Workstation. Softw., Pract. Exper. 15(11): 1103-1119 (1985)

Chris R. Jesshope: The Implementation of Fast Radix 2 Transforms on Array Processors. IEEE Trans. Computers 29(1): 20-27 (1980)

Chris R. Jesshope: Some Results Concerning Data Routing in Array Processors. IEEE Trans. Computers 29(7): 659-662 (1980)