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Jack S. N. Jean
2010 – today
- 2012
[j8]Fei Wang, Jack S. N. Jean: Architecture and operating system support for two-dimensional runtime partial reconfiguration. The Journal of Supercomputing 59(2): 610-635 (2012)- 2010
- [c13]Srikanth Nadella, Andrew Dittes, Jack S. N. Jean: Parameterized AND-OR Trees for FPGA Design Space Exploration. ERSA 2010: 255-258
2000 – 2009
- 2006
- [c12]
- 2005
- [c11]Fei Wang, Jack S. N. Jean, Shuxia Sun: Aspect Ratio Effects on Reconfigurable Computing. ERSA 2005: 71-77
- 2004
- [c10]Xinzhong Guo, Jack S. N. Jean: Design Enumeration of Mapping 2D FFT onto FPGA Based Reconfigurable Computers. ERSA 2004: 305-306
- 2003
- [j7]Xuejun Liang, Jack S. N. Jean: Mapping of generalized template matching onto reconfigurable computers. IEEE Trans. VLSI Syst. 11(3): 485-498 (2003)
- [c9]Jack S. N. Jean, Xinzhong Guo, Fei Wang, Lei Song, Ying Zhang: A Study of Mapping Generalized Sliding Window Operations on Reconfigurable Computers. Engineering of Reconfigurable Systems and Algorithms 2003: 51-57
- 2001
- [j6]Xuejun Liang, Jack S. N. Jean, Karen A. Tomko: Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems. The Journal of Supercomputing 19(1): 77-91 (2001)
- 2000
- [j5]Jack S. N. Jean, Xuejun Liang, Brian Drozd, Karen A. Tomko, Yan Wang: Automatic Target Recognition with Dynamic Reconfiguration. VLSI Signal Processing 25(1): 39-53 (2000)
- [c8]Xuejun Liang, Jack S. N. Jean: Interface Design for the Mapping of Generalized Template Matching on Reconfigurable Systems. PDPTA 2000
1990 – 1999
- 1999
- [j4]Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Jignesh Shah, Robert Cook: Dynamic Reconfiguration to Support Concurrent Applications. IEEE Trans. Computers 48(6): 591-602 (1999)
- [j3]Joseph A. Fernando, Jack S. N. Jean: Processor array design with FPGA area constraint. IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 253-264 (1999)
- [c7]Jack S. N. Jean, Xuejun Liang, Brian Drozd, Karen A. Tomko: Accelerating an IR Automatic Target Recognition Application with FPGAs. FCCM 1999: 290-291
- [c6]Jack S. N. Jean, Xuejun Liang, Karen A. Tomko: Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems. PDPTA 1999: 1111-1117
- 1998
- [c5]Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Robert Cook, Jignesh Shah: Dynamic Reconfiguration to Support Concurrent Applications. FCCM 1998: 302-303
- [c4]Hong K. Kim, Jack S. N. Jean: Parallel Optimistic Logic Simulation with Event Lookahead. ICPP 1998: 20-27
- 1996
- [c3]Hong K. Kim, Jack S. N. Jean: Concurrency Preserving Rartitioning (CPP) for Parallel Logic Simulation. Workshop on Parallel and Distributed Simulation 1996: 98-105
- 1995
- [c2]
- 1994
- [j2]Jin Wang, Jack S. N. Jean: Segmentation of merged characters by neural networks and shortest path. Pattern Recognition 27(5): 649-658 (1994)
- 1993
- [j1]Jin Wang, Jack S. N. Jean: Resolving multifont character confusion with neural networks. Pattern Recognition 26(1): 175-187 (1993)
- [c1]
Coauthor Index
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last updated on 2012-09-26 07:19 CEST by the dblp team