Tohru Ishihara

Lovic Gauthier, Tohru Ishihara: Processor Energy Characterization for Compiler-Assisted Software Energy Reduction. J. Electrical and Computer Engineering 2012 (2012)

Kyungsoo Lee, Tohru Ishihara: I/O aware task scheduling for energy harvesting embedded systems with PV and capacitor arrays. ESTImedia 2012: 48-55

Ji Gu, Tohru Ishihara, Kyungsoo Lee: Loop instruction caching for energy-efficient embedded multitasking processors. ESTImedia 2012: 97-106

Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera: A flexible structure of standard cell and its optimization method for near-threshold voltage operation. ICCD 2012: 235-240

Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera: A Standard Cell Optimization Method for Near-Threshold Voltage Operations. PATMOS 2012: 32-41

Kyungsoo Lee, Tohru Ishihara: A Dynamic Reconfiguration Technique for PV and Capacitor Arrays to Improve the Efficiency in Energy Harvesting Embedded Systems. SMARTGREENS 2012: 175-182

Ji Gu, Tohru Ishihara: A Case Study of Energy-efficient Loop Instruction Cache Design for Embedded Multitasking Systems. SMARTGREENS 2012: 197-202

Lovic Gauthier, Tohru Ishihara: Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications. IEICE Transactions 94-A(12): 2597-2608 (2011)

Maziar Goudarzi, Tohru Ishihara, Hamid Noori: Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies. T. HiPEAC 3: 275-299 (2011)

Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Shunitsu Kohara, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada: An integrated optimization framework for reducing the energy consumption of embedded real-time applications. ISLPED 2011: 271-276

Takumi Okuhira, Tohru Ishihara: Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits. PATMOS 2011: 237-246

Tohru Ishihara: A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems. IEICE Transactions 93-A(12): 2533-2541 (2010)

Maziar Goudarzi, Tohru Ishihara: SRAM Leakage Reduction by Row/Column Redundancy Under Random Within-Die Delay Variation. IEEE Trans. VLSI Syst. 18(12): 1660-1671 (2010)

Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura: Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories. Signal Processing Systems 60(2): 211-224 (2010)

Lovic Gauthier, Tohru Ishihara, Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada: Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems. CASES 2010: 157-166

Naotaka Maruyama, Tohru Ishihara, Hiroto Yasuura: An RTOS in hardware for energy efficient software-based TCP/IP processing. SASP 2010: 58-63

Lovic Gauthier, Tohru Ishihara: Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories. ESTImedia 2009: 116-125

Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami: Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems. IEICE Transactions 91-C(4): 410-417 (2008)

Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara: Way-Scaling to Reduce Power of Cache with Delay Variation. IEICE Transactions 91-A(12): 3576-3584 (2008)

Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura: A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die V_th variation. Microelectronics Journal 39(12): 1797-1808 (2008)

Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Tohru Ishihara: A Generalized Framework for System-Wide Energy Savings in Hard Real-Time Embedded Systems. EUC (1) 2008: 206-213

Maziar Goudarzi, Tohru Ishihara: Instruction cache leakage reduction by changing register operands and using asymmetric sram cells. ACM Great Lakes Symposium on VLSI 2008: 383-386

Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura: Simultaneous optimization of memory configuration and code allocation for low power embedded systems. ACM Great Lakes Symposium on VLSI 2008: 403-406

Maziar Goudarzi, Tohru Ishihara, Hamid Noori: Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation. HiPEAC 2008: 224-239

Maziar Goudarzi, Tohru Ishihara: Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation. ISLPED 2008: 93-98

Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara: Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways. ISVLSI 2008: 447-450

Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura: Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. PATMOS 2008: 62-71

Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato: AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications. SASP 2008: 83-88

Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami: Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems. IEICE Transactions 90-C(10): 1983-1991 (2007)

Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura: A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. ASP-DAC 2007: 878-883

Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami: Task scheduling for reliable cache architectures of multiprocessor systems. DATE 2007: 1490-1495

Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura: Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories. ESTImedia 2007: 13-18

Tohru Ishihara, Farzan Fallah: A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors. CoRR abs/0710.4703 (2007)

Donghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah: An Energy Characterization Framework for Software-Based Embedded Systems. ESTImedia 2006: 59-64

Makoto Sugihara, Tohru Ishihara, Masanori Muroyama, Koji Hashimoto: A Simulation-Based Soft Error Estimation Methodology for Computer Systems. ISQED 2006: 196-203

Tohru Ishihara, Farzan Fallah: A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors. DATE 2005: 358-363

Tohru Ishihara, Farzan Fallah: A cache-defect-aware code placement algorithm for improving the performance of processors. ICCAD 2005: 995-1001

Tohru Ishihara: Energy-Efficient Embedded System Design at 90nm and Below - A System-Level Perspective -. ISHPC 2005: 452-465

Tohru Ishihara, Farzan Fallah: A non-uniform cache architecture for low power system design. ISLPED 2005: 363-368

Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada: Comparative Study On Verilog-Based And C-Based Hardware Design Education. MSE 2003: 41-42

Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura: A Power Minimization Technique for Arithmetic Circuits by Cell Selection. VLSI Design 2002: 268-273

Tohru Ishihara, Kunihiro Asada: An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. VLSI Design 2002: 282-287

Takanori Okuma, Hiroto Yasuura, Tohru Ishihara: Software Energy Reduction Techniques for Variable-Voltage Processors. IEEE Design & Test of Computers 18(2): 31-41 (2001)

Tohru Ishihara, Kunihiro Asada: A system level memory power optimization technique using multiple supply and threshold voltages. ASP-DAC 2001: 456-461

Akihiko Inoue, Tohru Ishihara, Hiroto Yasuura: Flexible System LSI for Embedded Systems and Its Optimization Techniques. Design Autom. for Emb. Sys. 5(2): 179-205 (2000)

Tohru Ishihara, Hiroto Yasuura: A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. DATE 2000: 617-623

Koji Inoue, Tohru Ishihara, Kazuaki Murakami: Way-predicting set-associative cache for high performance and low energy consumption. ISLPED 1999: 273-275

Takanori Okuma, Tohru Ishihara, Hiroto Yasuura: Real-Time Task Scheduling for a Variable Voltage Processor. ISSS 1999: 24-29

Tohru Ishihara, Hiroto Yasuura: Power-Pro: Programmable Power Management Architecture. ASP-DAC 1998: 321-322

Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura: Instruction Scheduling for Power Reduction in Processor-Based System Design. DATE 1998: 855-860

Tohru Ishihara, Hiroto Yasuura: Voltage scheduling problem for dynamically variable voltage processors. ISLPED 1998: 197-202

Tohru Ishihara, Hiroto Yasuura: Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. ISLPED 1996: 117-120

Tohru Ishihara, Masakazu Kojima: On the big Mu in the affine scaling algorithm. Math. Program. 62: 85-93 (1993)