Masahiro Iida

Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi: A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). FPGA 2013: 271

Masahiro Iida, Motoki Amagasaki, Yasuhiro Okamoto, Qian Zhao, Toshinori Sueyoshi: COGRE: A Novel Compact Logic Cell Architecture for Area Minimization. IEICE Transactions 95-D(2): 294-302 (2012)

Kazuki Inoue, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi: An Easily Testable Routing Architecture and Prototype Chip. IEICE Transactions 95-D(2): 303-313 (2012)

Yoshihiro Ichinomiya, Tsuyoshi Kimura, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi: Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration. IEICE Transactions 95-A(12): 2347-2356 (2012)

Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi: Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams. FCCM 2012: 241

Kazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi: Fault detection and avoidance of FPGA in various granularities. FPL 2012: 539-542

Yoshihiro Ichinomiya, Kohei Takano, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi: Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration. FPT 2012: 220-223

Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi: A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration. ICA3PP (1) 2012: 139-152

Makoto Fujino, Hiroki Tanaka, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi: Fault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration. ICA3PP (1) 2012: 392-404

Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi: A novel physical defects recovery technique for FPGA-IP cores. ReConFig 2012: 1-7

Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi: Evaluation of fault tolerant technique based on homogeneous FPGA architecture. VLSI-SoC 2012: 225-230

Qian Zhao, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems. Embedded Systems Letters 3(3): 89-92 (2011)

Masahiro Iida, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi: A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. IEICE Transactions 94-C(4): 548-556 (2011)

Hiroomi Sawada, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: Parallelization of the channel width search for FPGA routing. SIGARCH Computer Architecture News 39(4): 82-85 (2011)

Qian Zhao, Yusuke Iwai, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: A novel reconfigurable logic device base on 3D stack technology. 3DIC 2011: 1-4

Kazuki Inoue, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: An Easily Testable Routing Architecture and Efficient Test Technique. FPL 2011: 291-294

Masahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi: An easily testable routing architecture of FPGA. VLSI-SoC 2011: 106-109

Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core. TRETS 4(1): 5 (2010)

Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi: Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration. FCCM 2010: 47-54

Masahiro Koga, Masahiro Iida, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi: First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. FPL 2010: 298-303

Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization. FPL 2010: 304-309

Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: A robust reconfigurable logic device based on less configuration memory logic cell. FPT 2010: 162-169

Shoichi Nishida, Jyunya Eto, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi: Power-aware FPGA routing fabrics and design tools. VLSI-SoC 2010: 67-72

Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: A Novel Local Interconnect Architecture for Variable Grain Logic Cell. ARC 2009: 97-109

Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi: Improvement of Execution Efficiency on the MX Core. PDCAT 2009: 420-425

Motoki Amagasaki, Ryoichi Yamaguchi, Masahiro Koga, Masahiro Iida, Toshinori Sueyoshi: An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture. Int. J. Reconfig. Comp. 2008 (2008)

Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi: A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices. IEICE Transactions 90-D(12): 1986-1989 (2007)

Kazunori Matsuyama, Motoki Amagasaki, Hideaki Nakayama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi: Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping. ARC 2007: 142-154

Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi: A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic. FCCM 2007: 285-286

Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi: A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic. FCCM 2007: 309-310

Motoki Amagasaki, Ryoichi Yamaguchi, Kazunori Matsuyama, Masahiro Iida, Toshinori Sueyoshi: A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores. FPL 2007: 550-553

Yoshiaki Satou, Motoki Amagasaki, Hiroshi Miura, Kazunori Matsuyama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi: An Embedded Reconfigurable Logic Core based on Variable Grain Logic Cell Architecture. FPT 2007: 241-244

Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi: Effective clustering technique to optimize routability of outer cluster nets. FPGA 2006: 229

Motoki Amagasaki, Takurou Shimokawa, Kazunori Matsuyama, Ryoichi Yamaguchi, Hideaki Nakayama, Naoto Hamabe, Masahiro Iida, Toshinori Sueyoshi: Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device. VLSI-SoC 2006: 198-203

Hisashi Tsukiashi, Masahiro Iida, Toshinori Sueyoshi: Applying the Small-World Network to Routing Structure of FPGAs. FPL 2005: 65-70