| 2012 | ||
|---|---|---|
| j5 | Gary A. Van Huben, K. D. Lamb, R. Brett Tremaine, B. E. Aleman, S. M. Rubow, S. H. Rider, Warren E. Maule, Michael E. Wazlowski: Server-class DDR3 SDRAM memory buffer chip. IBM Journal of Research and Development 56(1): 3 (2012) | |
| 2007 | ||
| j4 | Derrin M. Berger, Jonathan Y. Chen, Frank D. Ferraiolo, Jeffrey A. Magee, Gary A. Van Huben: High-speed source-synchronous interface for the IBM System z9 processor. IBM Journal of Research and Development 51(1/2): 53-64 (2007) | |
| c2 | Adrian E. Seigler, Gary A. Van Huben, Hari Mony: Formal Verification of Partial Good Self-Test Fencing Structures. FMCAD 2007: 188-191 | |
| 2006 | ||
| c1 | Tilman Glökler, Jason Baumgartner, Devi Shanmugam, A. E. (Rick) Seigler, Gary A. Van Huben, Barinjato Ramanandray, Hari Mony, Paul Roessler: Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning. FMCAD 2006: 3-10 | |
| 2004 | ||
| j3 | Pak-kin Mak, Gary E. Strait, Michael A. Blake, Kevin W. Kark, Vesselina K. Papazova, A. E. (Rick) Seigler, Gary A. Van Huben, Liyong Wang, George C. Wellwood: Processor subsystem interconnect architecture for a large symmetric multiprocessing system. IBM Journal of Research and Development 48(3-4): 323-338 (2004) | |
| 1999 | ||
| j2 | Gary A. Van Huben, Timothy G. McNamara, Thomas E. Gilbert: PLL modeling and verification in a cycle-simulation environment. IBM Journal of Research and Development 43(5): 915-926 (1999) | |
| 1997 | ||
| j1 | Gary A. Van Huben: The role of two-cycle simulation in the S/390 verification process. IBM Journal of Research and Development 41(4&5): 593-600 (1997) | |
Colors in the list of coauthors
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