Pingli Huang

Wenbo Liu, Pingli Huang, Yun Chiu: A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration. CICC 2012: 1-4

Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu: SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration. J. Solid-State Circuits 46(8): 1893-1903 (2011)

Wenbo Liu, Pingli Huang, Yun Chiu: A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration. J. Solid-State Circuits 46(11): 2661-2672 (2011)

Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu: SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration. CICC 2010: 1-4

Wenbo Liu, Pingli Huang, Yun Chiu: A 12b 22.5/45MS/s 3.0mW 0.059mm² CMOS SAR ADC achieving over 90dB SFDR. ISSCC 2010: 380-381

Pingli Huang, Yun Chiu: A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs. ISCAS 2007: 1241-1244