| 2013 | ||
|---|---|---|
| j4 | Hsin-Hsiung Huang, Juing-Huei Su, Chyi-Shyong Lee: A Contest-Oriented Project for Learning Intelligent Mobile Robots. IEEE Trans. Education 56(1): 88-97 (2013) | |
| 2011 | ||
| j3 | Hsin-Hsiung Huang, Jui-Hung Hung, Cheng-Chiang Lin, Tsai-Ming Hsieh: Wire Planning for Electromigration and Interference Avoidance in Analog Circuits. IEICE Transactions 94-A(11): 2402-2411 (2011) | |
| j2 | Hsin-Hsiung Huang, Yi-Ren Yeh: An iterative algorithm for robust kernel principal component analysis. Neurocomputing 74(18): 3921-3930 (2011) | |
| c6 | Juing-Huei Su, Chyi-Shyong Lee, Hsin-Hsiung Huang, Shih-Wei Chao, Sheng-Hong Lin, Yu-Cheng Wu: A Versatile Kit for Teaching Intelligent Mobile Robots. FIRA RoboWorld Congress 2011: 42-49 | |
| 2010 | ||
| j1 | Hsi-An Chien, Cheng-Chiang Lin, Hsin-Hsiung Huang, Tsai-Ming Hsieh: Optimal Supply Voltage Assignment under Timing, Power and Area Constraints. IEICE Transactions 93-A(4): 761-768 (2010) | |
| 2008 | ||
| c5 | Hsin-Hsiung Huang, Hui-Yu Huang, Yu-Cheng Lin, Tsai-Ming Hsieh: Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system. ISCAS 2008: 1200-1203 | |
| c4 | Hsin-Hsiung Huang, Shu-Ping Chang, Yu-Cheng Lin, Tsai-Ming Hsieh: Timing-driven X-architecture router among rectangular obstacles. ISCAS 2008: 1804-1807 | |
| 2006 | ||
| c3 | Hsin-Hsiung Huang, Yung-Ching Chen, Tsai-Ming Hsieh: A congestion-driven buffer planner with space reservation. ISCAS 2006 | |
| 2005 | ||
| c2 | Chin-Hui Wang, Yung-Ching Chen, Tsai-Ming Hsieh, Chih-Hung Lee, Hsin-Hsiung Huang: A new congestion and crosstalk aware router. ISCAS (6) 2005: 6234-6237 | |
| 2002 | ||
| c1 | Chih-Hung Lee, Yu-Chung Lin, Hsin-Hsiung Huang, Tsai-Ming Hsieh: Structural Decomposition with Functional Considerations for Low Power. ISQED 2002: 464-469 | |
Colors in the list of coauthors
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