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 | 2012 | |
|---|---|---|
| j10 |      | Hong-Yi Huang, Shiun-Dian Jan, Yang Chou, Cheng-Yu Chen: CMOS Differential Circuits Using Charge-Redistribution and Reduced-Swing Schemes. IEICE Transactions 95-C(2): 275-283 (2012) |
| j9 | | Hong-Yi Huang, Chun-Chieh Wu, Ching-Hsing Luo: An MICS band frequency synthesizer using active inductor and auto-calibration scheme. Microelectronics Journal 43(8): 592-599 (2012) |
| j8 | | Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang: A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator. IEEE Trans. on Circuits and Systems 59-II(12): 888-892 (2012) |
| c25 | | Yi-Hsiang Juan, Ching-Hsing Luo, Hong-Yi Huang: A low voltage sigma delta modulator for temperature sensor. DDECS 2012: 270-273 |
| 2011 | ||
| j7 | | Hong-Yi Huang, Ruei-Iun Pu: Differential bidirectional transceiver for on-chip long wires. Microelectronics Journal 42(11): 1208-1215 (2011) |
| j6 | | Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang, Yu-Liang Li, Yong-Jhen Jhu: A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler. IEEE Trans. on Circuits and Systems 58-II(8): 492-496 (2011) |
| j5 | | Shih-Lun Chen, Hong-Yi Huang, Ching-Hsing Luo: A Low-Cost High-Quality Adaptive Scalar for Real-Time Multimedia Applications. IEEE Trans. Circuits Syst. Video Techn. 21(11): 1600-1611 (2011) |
| j4 | | Shih-Lun Chen, Hong-Yi Huang, Ching-Hsing Luo: Time Multiplexed VLSI Architecture for Real-Time Barrel Distortion Correction in Video-Endoscopic Images. IEEE Trans. Circuits Syst. Video Techn. 21(11): 1612-1621 (2011) |
| c24 | | Tzu-Chi Huang, Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng, Ching-Hsing Luo: All digital phase-locked loop using active inductor oscillator and novel locking algorithm. ISCAS 2011: 486-489 |
| 2010 | ||
| j3 | | Shiann-Rong Kuang, Jiun-Ping Wang, Hong-Yi Huang: Variable-Latency Floating-Point Multipliers for Low-Power Applications. IEEE Trans. VLSI Syst. 18(10): 1493-1497 (2010) |
| c23 | | Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang: A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. DDECS 2010: 285-288 |
| 2009 | ||
| j2 | | Shih-Lun Chen, Ho-Yin Lee, Chiung-An Chen, Hong-Yi Huang, Ching-Hsing Luo: Wireless Body Sensor Network With Adaptive Low-Power Design for Biometrics and Healthcare Applications. IEEE Systems Journal 3(4): 398-409 (2009) |
| c22 | | Hong-Yi Huang, Fu-Chien Tsai: Analysis and optimization of ring oscillator using sub-feedback scheme. DDECS 2009: 28-29 |
| c21 | | Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng: 0.5V 160-MHz 260uW all digital phase-locked loop. DDECS 2009: 186-193 |
| 2008 | ||
| c20 | | Wei-Chen Huang, Chen-Ming Hsu, Chien-Ming Lee, Hong-Yi Huang, Ching-Hsing Luo: Dual band LNA/mixer using conjugate matching for implantable biotelemetry. ISCAS 2008: 1764-1767 |
| c19 | | Hong-Yi Huang, Chia-Ming Liang, Shi-Jia Sun: Low-power 50% duty cycle corrector. ISCAS 2008: 2362-2365 |
| c18 | | Hong-Yi Huang, Li-Wei Huang, Wei-Sheng Tseng, Chih-Yuan Hsu: A 6-Gbit/s SATA spread-spectrum clock generator using two-stage delta-sigma modulator. SoCC 2008: 333-336 |
| c17 | | Hong-Yi Huang, Yi-Jui Tsai, Kung-Liang Ho, Chan-Yu Lin: All digital time-to-digital converter using single delay-locked loop. SoCC 2008: 341-344 |
| 2007 | ||
| c16 | | Hong-Yi Huang, Sheng-Da Wu, Yi-Jui Tsai: A New Cycle-Time-to-Digital Converter With Two Level Conversion Scheme. ISCAS 2007: 2160-2163 |
| 2006 | ||
| c15 | | Hong-Yi Huang, Chia-Ming Liang, Wei-Ming Chiu: 1-99% input duty 50% output duty cycle corrector. ISCAS 2006 |
| c14 | | Hong-Yi Huang, Bo-Ruei Wang, Jen-Chieh Liu: High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit. ISCAS 2006 |
| c13 | | |
| 2005 | ||
| c12 | | Hong-Yi Huang, Sheng-Fen Ho, Li-Wei Huang: A 64-MHz/spl sim/1920-MHz programmable spread-spectrum clock generator. ISCAS (4) 2005: 3363-3366 |
| 2004 | ||
| j1 | | Hong-Yi Huang, Shih-Lun Chen: Interconnect accelerating techniques for sub-100-nm gigascale systems. IEEE Trans. VLSI Syst. 12(11): 1192-1200 (2004) |
| c11 | | Chun-Jen Huang, Hong-Yi Huang: A low-voltage CMOS rail-to-rail operational amplifier using double p-channel differential input pairs. ISCAS (1) 2004: 673-676 |
| 2003 | ||
| c10 | | Chin-Shan Hsieh, Hong-Yi Huang, Jeng-Dang Juan, Ruey-Nan Yeh: A high-bandwidth wireless infrared receiver with feedforward offset extractor. ISCAS (1) 2003: 73-76 |
| 2002 | ||
| c9 | | Hong-Yi Huang, Shih-Lun Chen: Threshold triggers and accelerator for deep submicron interconnection. APCCAS (2) 2002: 143-146 |
| c8 | | |
| c7 | | |
| c6 | | |
| c5 | | |
| 2001 | ||
| c4 | | Hong-Yi Huang, Teng-Neng Wang: High-speed CMOS logic circuits in capacitor coupling technique. ISCAS (4) 2001: 634-637 |
| 1995 | ||
| c3 |  | Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu: Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. ISCAS 1995: 1572-1575 |
| 1994 | ||
| c2 | | Hong-Yi Huang, Chung-Yu Wu: New CMOS Differential Logic Circuits for True-Single-Phase Pipelined Systems. ISCAS 1994: 15-18 |
| 1993 | ||
| c1 | | Hong-Yi Huang, Chung-Yu Wu: Redundant Algebra and Integrated Circuit Implementation of Ternary Logic and Their Applications. ISCAS 1993: 1905-1908 |
Colors in the list of coauthors
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