| 2010 | ||
|---|---|---|
| c2 | Charles L. Johnson, David H. Allen, Jeffrey D. Brown, Steve Vanderwiel, Russ Hoover, Heather D. Achilles, Chen-Yong Cher, George A. May, Hubertus Franke, Jimi Xenidis, Claude Basso: A wire-speed powerTM processor: 2.3GHz 45nm SOI with 16 cores and 64 threads. ISSCC 2010: 104-105 | |
| 2000 | ||
| c1 | Cindy Eisner, Irit Shitsevalov, Russ Hoover, Wayne G. Nation, Kyle L. Nelson, Ken Valk: A methodology for formal design of hardware control with application to cache coherence protocols. DAC 2000: 724-729 | |
Colors in the list of coauthors
Last update Sun May 19 22:43:01 2013 CET by the DBLP Team —
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