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Yoshinobu Higami
2010 – today
- 2013
[j16]Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja: Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment. IEICE Transactions 96-D(6): 1323-1331 (2013)- 2012
- [j15]Yoshinobu Higami, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo: Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool. IEICE Transactions 95-D(4): 1093-1100 (2012)
- [j14]Dewiani, Kouji Hirata, Khamisi Kalegele, Yoshinobu Higami, Shin-ya Kobayashi: Dynamic Routing and Wavelength Assignment with Backward Reservation in Wavelength-routed Multifiber WDM Networks. JNW 7(9): 1441-1448 (2012)
- [c32]Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja: Diagnosis for Bridging Faults on Clock Lines. PRDC 2012: 135-144
- 2011
- [c31]Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja: Fault simulation and test generation for clock delay faults. ASP-DAC 2011: 799-805
- [c30]Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja: On Detecting Transition Faults in the Presence of Clock Delay Faults. Asian Test Symposium 2011: 1-6
- [c29]Yoshinobu Higami, Hiroshi Furutani, Takao Sakai, Shuichi Kameyama, Hiroshi Takahashi: Test Pattern Selection for Defect-Aware Test. Asian Test Symposium 2011: 102-107
- [c28]Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja: Enhancement of Clock Delay Faults Testing. European Test Symposium 2011: 216
- 2010
- [j13]Kouji Hirata, Khamisi Kalegele, Yoshinobu Higami, Shin-ya Kobayashi: Dynamic Parallel Downloading with Network Coding in $\lambda$-Grid Networks. JCM 5(5): 425-435 (2010)
- [j12]Kouji Hirata, Khamisi Kalegele, Yoshinobu Higami, Shin-ya Kobayashi: Replica Selection and Downloading based on Wavelength Availability in λ-grid Networks. JCM 5(9): 692-702 (2010)
2000 – 2009
- 2009
- [j11]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu: Addressing Defect Coverage through Generating Test Vectors for Transistor Defects. IEICE Transactions 92-A(12): 3128-3135 (2009)
- [c27]Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume: New Class of Tests for Open Faults with Considering Adjacent Lines. Asian Test Symposium 2009: 301-306
- [c26]Yoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo, Yuzo Takamatsu: Diagnostic test generation for transition faults using a stuck-at ATPG tool. ITC 2009: 1-9
- [c25]Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume: A Novel Approach for Improving the Quality of Open Fault Diagnosis. VLSI Design 2009: 85-90
- [c24]Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu: Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. VLSI Design 2009: 91-96
- 2008
- [j10]Yuzo Takamatsu, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Koji Yamazaki: Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information. IEICE Transactions 91-D(3): 675-682 (2008)
- [j9]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu: Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools. IEICE Transactions 91-D(3): 690-699 (2008)
- [j8]Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato: Post-BIST Fault Diagnosis for Multiple Faults. IEICE Transactions 91-D(3): 771-775 (2008)
- [j7]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu: Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors. IEICE Transactions 91-A(12): 3506-3513 (2008)
- 2007
- [c23]Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu: Timing-Aware Diagnosis for Small Delay Defects. DFT 2007: 223-234
- [c22]Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume: Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines. DFT 2007: 243-251
- [c21]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu: Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. VLSI Design 2007: 781-786
- 2006
- [j6]Yoshinobu Higami, Seiji Kajihara, Irith Pomeranz, Shin-ya Kobayashi, Yuzo Takamatsu: On Finding Don't Cares in Test Sequences for Sequential Circuits. IEICE Transactions 89-D(11): 2748-2755 (2006)
- [c20]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu: Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. ASP-DAC 2006: 659-664
- [c19]Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato: Effective Post-BIST Fault Diagnosis for Multiple Faults. DFT 2006: 401-109
- 2005
- [j5]Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu: Test cost reduction for logic circuits: Reduction of test data volume and test application time. Systems and Computers in Japan 36(6): 69-83 (2005)
- [c18]T. Seiyama, Hiroshi Takahashi, Yoshinobu Higami, Kazuo Yamazaki, Yuzo Takamatsu: On the fault diagnosis in the presence of unknown fault models using pass/fail information. ISCAS (3) 2005: 2987-2990
- 2004
- [j4]Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu: Generation of Test Sequences with Low Power Dissipation for Sequential Circuits. IEICE Transactions 87-D(3): 530-536 (2004)
- [c17]Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu: Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction. Asian Test Symposium 2004: 46-49
- [c16]Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu: Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set. Asian Test Symposium 2004: 216-221
- [c15]Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu: Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests. Asian Test Symposium 2004: 222-227
- 2003
- [c14]Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz: A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. ICCD 2003: 397-
- 2002
- [c13]Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu: A Method to Reduce Power Dissipation during Test for Sequential Circuits. Asian Test Symposium 2002: 326-331
- [c12]Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu: Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits. DELTA 2002: 431-433
- 2001
- [c11]Hiroshi Takahashi, Marong Phadoongsidhi, Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu: Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits. Asian Test Symposium 2001: 63-
- [c10]Yoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu: Test Generation for Double Stuck-at Faults. Asian Test Symposium 2001: 71-75
- 2000
- [j3]Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita: Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits. J. Electronic Testing 16(5): 443-451 (2000)
- [j2]Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita: Static test compaction for IDDQ testing of bridging faults in sequential circuits. Systems and Computers in Japan 31(11): 41-50 (2000)
- [c9]Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita: Fault models and test generation for IDDQ testing: embedded tutorial. ASP-DAC 2000: 509-514
- [c8]Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita: Test sequence compaction for sequential circuits with reset states. Asian Test Symposium 2000: 165-170
1990 – 1999
- 1999
- [c7]Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita: Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium 1999: 141-146
- [c6]Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita: Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. VLSI Design 1999: 72-77
- 1998
- [c5]Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita: Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits. Asian Test Symposium 1998: 312-317
- 1997
- [c4]
- 1996
- [c3]Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique. Asian Test Symposium 1996: 94-99
- 1995
- [j1]Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Partial scan design and test sequence generation based on reduced scan shift method. J. Electronic Testing 7(1-2): 115-124 (1995)
- [c2]Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Test sequence compaction by reduced scan shift and retiming. Asian Test Symposium 1995: 169-175
- 1994
- [c1]Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Reduced Scan Shift: A New Testing Method for Sequential Circuit. ITC 1994: 624-630
Coauthor Index
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last updated on 2013-06-18 22:12 CEST by the dblp team