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Pavan Kumar Hanumolu
2010 – today
- 2013
[j18]Ramin Zanbaghi, Pavan Kumar Hanumolu, Terri S. Fiez: An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW. J. Solid-State Circuits 48(2): 487-501 (2013)- [j17]Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu: Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops. J. Solid-State Circuits 48(6): 1416-1428 (2013)
- [c32]Tejasvi Anand, Mrunmay Talegaonkar, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu: A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time. ISSCC 2013: 256-257
- 2012
- [j16]Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu: A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer. J. Solid-State Circuits 47(12): 2916-2927 (2012)
- [j15]Brian Drost, Mrunmay Talegaonkar, Pavan Kumar Hanumolu: Analog Filter Design Using Ring Oscillator Integrators. J. Solid-State Circuits 47(12): 3120-3129 (2012)
- [j14]Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez: A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ Modulator With Multirated VCO-Based ADC. IEEE Trans. on Circuits and Systems 59-I(8): 1604-1613 (2012)
- [j13]Naga Sasidhar, David Gubbins, Pavan Kumar Hanumolu, Un-Ku Moon: Rail-to-Rail Input Pipelined ADC Incorporating Multistage Signal Mapping. IEEE Trans. on Circuits and Systems 59-II(9): 558-562 (2012)
- [c31]Tao Tong, Wenhuan Yu, Pavan Kumar Hanumolu, Gabor C. Temes: Calibration technique for SAR analog-to-digital converters. ISCAS 2012: 2993-2996
- [c30]Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu: A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer. ISSCC 2012: 152-154
- [c29]Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu: A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC. ISSCC 2012: 242-244
- [c28]Brian Drost, Mrunmay Talegaonkar, Pavan Kumar Hanumolu: A 0.55V 61dB-SNR 67dB-SFDR 7MHz 4th-order Butterworth filter using ring-oscillator-based integrators in 90nm CMOS. ISSCC 2012: 360-362
- [c27]Amr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu: A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators. ISSCC 2012: 464-466
- [c26]Pavan Kumar Hanumolu, Un-Ku Moon, Terri S. Fiez: Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques. VLSI Design 2012: 20-21
- 2011
- [j12]Wenjing Yin, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu: A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking. J. Solid-State Circuits 46(8): 1870-1880 (2011)
- [j11]Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu: A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration. J. Solid-State Circuits 46(12): 2759-2771 (2011)
- [j10]Sachin Rao, Qadeer Khan, Sarvesh Bang, Damian Swank, Arun Rao, William McIntyre, Pavan Kumar Hanumolu: A 1.2-A Buck-Boost LED Driver With On-Chip Error Averaged SenseFET-Based Current Sensing Technique. J. Solid-State Circuits 46(12): 2772-2783 (2011)
- [j9]Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu: A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance. J. Solid-State Circuits 46(12): 3150-3162 (2011)
- [j8]Wenjing Yin, Rajesh Inti, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu: A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery. J. Solid-State Circuits 46(12): 3163-3173 (2011)
- [j7]Igor Vytyaz, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram: Design-Oriented Analysis of Circuits With Equality Constraints. IEEE Trans. on Circuits and Systems 58-I(5): 1089-1098 (2011)
- [j6]Yan Wang, Pavan Kumar Hanumolu, Gabor C. Temes: Design Techniques for Wideband Discrete-Time Delta-Sigma ADCs With Extra Loop Delay. IEEE Trans. on Circuits and Systems 58-I(7): 1518-1530 (2011)
- [c25]Ankur Agrawal, Pavan Kumar Hanumolu, Gu-Yeon Wei: Area efficient phase calibration of a 1.6 GHz multiphase DLL. CICC 2011: 1-4
- [c24]Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez: A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer. CICC 2011: 1-4
- [c23]Sanghyeon Lee, Jeongseok Chae, Mitsuru Aniya, Seiji Takeuchi, Koichi Hamashita, Pavan Kumar Hanumolu, Gabor C. Temes: A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application. CICC 2011: 1-4
- [c22]Mrunmay Talegaonkar, Rajesh Inti, Pavan Kumar Hanumolu: Digital clock and data recovery circuit design: Challenges and tradeoffs. CICC 2011: 1-8
- [c21]Bangda Yang, Brian Drost, Sachin Rao, Pavan Kumar Hanumolu: A high-PSR LDO using a feedforward supply-noise cancellation technique. CICC 2011: 1-4
- [c20]Qadeer Khan, Sachin Rao, Damian Swank, Arun Rao, William McIntyre, Sarvesh Bang, Pavan Kumar Hanumolu: A 3.3V 500mA digital Buck-Boost converter with 92% peak efficiency using constant ON/OFF time delta-sigma fractional-N control. ESSCIRC 2011: 439-442
- [c19]Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu: A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration. ISSCC 2011: 92-94
- [c18]Rajesh Inti, Amr Elshazly, Brian Young, Wenjing Yin, Marcel A. Kossel, Thomas Toifl, Pavan Kumar Hanumolu: A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS. ISSCC 2011: 152-154
- [c17]Sachin Rao, Qadeer Khan, Sarvesh Bang, Damian Swank, Arun Rao, William McIntyre, Pavan Kumar Hanumolu: A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing. ISSCC 2011: 238-240
- [c16]Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu: A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance. ISSCC 2011: 438-450
- [c15]Wenjing Yin, Rajesh Inti, Amr Elshazly, Pavan Kumar Hanumolu: A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery. ISSCC 2011: 440-442
- 2010
- [j5]David Gubbins, Bumha Lee, Pavan Kumar Hanumolu, Un-Ku Moon: Continuous-Time Input Pipeline ADCs. J. Solid-State Circuits 45(8): 1456-1468 (2010)
- [j4]Abhijith Arakali, Srikanth Gondi, Pavan Kumar Hanumolu: Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops. IEEE Trans. on Circuits and Systems 57-I(11): 2880-2889 (2010)
- [c14]Sarvesh Bang, Damian Swank, Arun Rao, William McIntyre, Qadeer Khan, Pavan Kumar Hanumolu: A 1.2A 2MHz tri-mode Buck-Boost LED driver with feed-forward duty cycle correction. CICC 2010: 1-4
- [c13]Jeongseok Chae, Sanghyeon Lee, Mitsuru Aniya, Seiji Takeuchi, Koichi Hamashita, Pavan Kumar Hanumolu, Gabor C. Temes: A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer. CICC 2010: 1-4
- [c12]Wenjing Yin, Rajesh Inti, Pavan Kumar Hanumolu: A 1.6mW 1.6ps-rms-jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS. CICC 2010: 1-4
- [c11]Brian Young, Sunwoo Kwon, Amr Elshazly, Pavan Kumar Hanumolu: A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth. CICC 2010: 1-4
2000 – 2009
- 2009
- [j3]Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram: Automated Design and Optimization of Low-Noise Oscillators. IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 609-622 (2009)
- [j2]Volodymyr Kratyuk, Pavan Kumar Hanumolu, Kerem Ok, Un-Ku Moon, Kartikeya Mayaram: A Digital PLL With a Stochastic Time-to-Digital Converter. IEEE Trans. on Circuits and Systems 56-I(8): 1612-1621 (2009)
- [c10]David Gubbins, Sunwoo Kwon, Bumha Lee, Pavan Kumar Hanumolu, Un-Ku Moon: A continuous-time input pipeline ADC with inherent anti-alias filtering. CICC 2009: 275-278
- [c9]
- [c8]Sunwoo Kwon, Pavan Kumar Hanumolu, Sang-Ho Kim, Sung-No Lee, Seung-Bin You, Ho-Jin Park, Jae-Whui Kim, Un-Ku Moon: An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing. CICC 2009: 171-174
- [c7]Skyler Weaver, Benjamin P. Hershberg, Pavan Kumar Hanumolu, Un-Ku Moon: A multiplexer-based digital passive linear counter (PLINCO). ICECS 2009: 607-610
- 2008
- [j1]Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram: Sensitivity Analysis for Oscillators. IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1521-1534 (2008)
- [c6]Igor Vytyaz, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram: Periodic Steady-State Analysis Augmented with Design Equality Constraints. DATE 2008: 312-317
- 2007
- [c5]Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram: Sensitivity analysis for oscillators. ICCAD 2007: 458-463
- 2006
- [c4]N. Talebbeydokhti, Pavan Kumar Hanumolu, Peter Kurahashi, Un-Ku Moon: Constant transconductance bias circuit with an on-chip resistor. ISCAS 2006
- 2005
- [c3]Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram: A low spur fractional-N frequency synthesizer architecture. ISCAS (3) 2005: 2807-2810
- [c2]Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram: An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications. ISCAS (4) 2005: 3986-3989
- 2004
- [c1]Pavan Kumar Hanumolu, Bryan Casper, Randy Mooney, Gu-Yeon Wei, Un-Ku Moon: Jitter in high-speed serial and parallel links. ISCAS (4) 2004: 425-428
Coauthor Index
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last updated on 2013-05-31 02:01 CEST by the dblp team