Mototsugu Hamada

Daisuke Miyashita, Hiroyuki Kobayashi, Jun Deguchi, Shouhei Kousai, Mototsugu Hamada, Ryuichi Fujimoto: A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter. IEICE Transactions 95-C(6): 1008-1016 (2012)

Shouhei Kousai, Daisuke Miyashita, Junji Wadatsumi, Rui Ito, Takahiro Sekiguchi, Mototsugu Hamada, Kenichi Okada: A Low-Noise and Highly-Linear Transmitter with Envelope Injection Pre-Power Amplifier for Multi-Mode Radio. IEICE Transactions 94-A(2): 592-602 (2011)

Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki: A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. J. Solid-State Circuits 46(1): 32-41 (2011)

Hiroyuki Kobayashi, Shouhei Kousai, Yoshiaki Yoshihara, Mototsugu Hamada: An all-digital 8-DPSK polar transmitter with second-order approximation scheme and phase rotation-constant digital PA for bluetooth EDR in 65nm CMOS. ISSCC 2011: 174-176

Chen Kong Teh, Tetsuya Fujita, Hiroyuki Hara, Mototsugu Hamada: A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS. ISSCC 2011: 338-340

Kenichi Agawa, Shin-ichiro Ishizuka, Hideaki Majima, Hiroyuki Kobayashi, Masayuki Koizumi, Takeshi Nagano, Makoto Arai, Yutaka Shimizu, Asuka Maki, Go Urakawa, Tadashi Terada, Nobuyuki Itoh, Mototsugu Hamada, Fumie Fujii, Tadamasa Kato, Sadayuki Yoshitomi, Nobuaki Otsuka: A 0.13 µm CMOS Bluetooth EDR Transceiver with High Sensitivity over Wide Temperature Range and Immunity to Process Variation. IEICE Transactions 93-C(6): 803-811 (2010)

Jun Deguchi, Daisuke Miyashita, Yosuke Ogasawara, Gaku Takemura, Masaomi Iwanaga, Kenichi Sami, Rui Ito, Junji Wadatsumi, Yuki Tsuda, Shoko Oda, Shunji Kawaguchi, Nobuyuki Itoh, Mototsugu Hamada: A Fully Integrated 2 ˟ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS. J. Solid-State Circuits 45(12): 2774-2784 (2010)

Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki: A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm. ISSCC 2010: 326-327

Jun Deguchi, Daisuke Miyashita, Yosuke Ogasawara, Gaku Takemura, Masaomi Iwanaga, Kenichi Sami, Rui Ito, Junji Wadatsumi, Yuki Tsuda, Shoko Oda, Shunji Kawaguchi, Nobuyuki Itoh, Mototsugu Hamada: A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS. ISSCC 2010: 456-457

Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura: A Novel Automatic Quality Factor Tuning Scheme for a Low-Power Wideband Active-RC Filter. IEICE Transactions 92-A(2): 411-420 (2009)

Nobuyuki Itoh, Mototsugu Hamada: RF-analog circuit design in scaled SoC. ASP-DAC 2009: 702-707

Jun Deguchi, Daisuke Miyashita, Mototsugu Hamada: A 0.6V 380µW -14dBm LO-input 2.4GHz double-balanced current-reusing single-gate CMOS mixer with cyclic passive combiner. ISSCC 2009: 224-225

Hideaki Majima, Mototsugu Hamada: A 90nm CMOS CT BPF for Bluetooth transceivers with DT 1b-switched-resistor cutoff-frequency control. ISSCC 2009: 334-335

Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki: An automated runtime power-gating scheme. ICCD 2007: 382-387

Yukihito Oowaki, Shinichiro Shiratake, Toshihide Fujiyoshi, Mototsugu Hamada, Fumitoshi Hatori, Masami Murakata, Masafumi Takahashi: Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI. IEICE Transactions 89-C(3): 263-270 (2006)

C. K. Teh, Mototsugu Hamada, Tetsuya Fujita, Hiroyuki Hara, N. Ikumi, Yukihito Oowaki: Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems. IEEE Trans. VLSI Syst. 14(12): 1379-1383 (2006)

Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda: Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques. DAC 1998: 483-488