Rajesh K. Gupta

Puneet Gupta, Yuvraj Agarwal, Lara Dolecek, Nikil Dutt, Rajesh K. Gupta, Rakesh Kumar, Subhasish Mitra, Alexandru Nicolau, Tajana Simunic Rosing, Mani B. Srivastava, Steven Swanson, Dennis Sylvester: Underdesigned and Opportunistic Computing in Presence of Hardware Variability. IEEE Trans. on CAD of Integrated Circuits and Systems 32(1): 8-23 (2013)

Muhammad Abdullah Adnan, Rajesh Gupta: Utility-aware deferred load balancing in the cloud driven by dynamic pricing of electricity. DATE 2013: 262-265

Abbas Rahimi, Andrea Marongiu, Paolo Burgio, Rajesh K. Gupta, Luca Benini: Variation-tolerant OpenMP tasking on tightly-coupled processor clusters. DATE 2013: 541-546

Abbas Rahimi, Luca Benini, Rajesh K. Gupta: Hierarchically focused guardbanding: an adaptive approach to mitigate PVT variations and aging. DATE 2013: 1695-1700

P. Glenn Gulak, Rajesh Gupta, Gianluca Setti, Yervant Zorian: Message From the Steering Committee. IEEE Design & Test of Computers 29(1): 5 (2012)

Yan Ma, Bin Gong, Ryo Sugihara, Rajesh Gupta: Energy-efficient deadline scheduling for heterogeneous systems. J. Parallel Distrib. Comput. 72(12): 1725-1740 (2012)

Muhammad Abdullah Adnan, Ryo Sugihara, Rajesh K. Gupta: Energy Efficient Geographical Load Balancing via Dynamic Deferral of Workload. IEEE CLOUD 2012: 188-195

Abbas Rahimi, Luca Benini, Rajesh K. Gupta: Analysis of instruction-level vulnerability to dynamic voltage and temperature variations. DATE 2012: 1102-1105

Abbas Rahimi, Luca Benini, Rajesh Gupta: Procedure hopping: a low overhead solution to mitigate variability in shared-L1 processor clusters. ISLPED 2012: 415-420

Alan Leung, Manish Gupta, Yuvraj Agarwal, Rajesh Gupta, Ranjit Jhala, Sorin Lerner: Verifying GPU kernels by test amplification. PLDI 2012: 383-394

Rajesh Gupta: Keynote Talk: The Variability Expeditions: Exploring the Software Stack for Underdesigned Computing Machines. VLSI Design 2012: 7-8

Nikil Dutt, Mani B. Srivastava, Rajesh Gupta, Subhasish Mitra: Tutorial T6: Variability-resistant Software and Hardware for Nano-Scale Computing. VLSI Design 2012: 22-24

Muhammad Abdullah Adnan, Ryo Sugihara, Rajesh Gupta: Energy Efficient Geographical Load Balancing via Dynamic Deferral of Workload. CoRR abs/1204.2320 (2012)

Devi Yalamarthy, Joel Coburn, Rajesh Gupta, Glen Edwards, Mark Kelly: Computational Mass Spectrometry in a Reconfigurable Coherent Coprocessing Architecture. IEEE Design & Test of Computers 28(4): 58-67 (2011)

Bridget Benson, Arash Arfaee, Choon Kim, Ryan Kastner, Rajesh K. Gupta: Integrating Embedded Computing Systems Into High School and Early Undergraduate Education. IEEE Trans. Education 54(2): 197-202 (2011)

Ryo Sugihara, Rajesh K. Gupta: Path Planning of Data Mules in Sensor Networks. TOSN 8(1): 1 (2011)

Joel Coburn, Adrian M. Caulfield, Ameen Akel, Laura M. Grupp, Rajesh K. Gupta, Ranjit Jhala, Steven Swanson: NV-Heaps: making persistent objects fast and safe with next-generation, non-volatile memories. ASPLOS 2011: 105-118

Puneet Gupta, Rajesh K. Gupta: Underdesigned and Opportunistic Computing. Asian Test Symposium 2011: 498-499

Yuvraj Agarwal, Thomas Weng, Rajesh K. Gupta: Understanding the role of buildings in a smart microgrid. DATE 2011: 1224-1229

Ryo Sugihara, Rajesh K. Gupta: Clock Synchronization with Deterministic Accuracy Guarantee. EWSN 2011: 130-146

Rahul Balani, Lucas Francisco Wanner, Jonathan Friedman, Mani B. Srivastava, Kaisen Lin, Rajesh K. Gupta: Programming Support for Distributed Optimization and Control in Cyber-Physical Systems. ICCPS 2011: 109-118

Ryo Sugihara, Rajesh K. Gupta: Sensor localization with deterministic accuracy guarantee. INFOCOM 2011: 1772-1780

Yuvraj Agarwal, Bharathan Balaji, Seemanta Dutta, Rajesh K. Gupta, Thomas Weng: Duty-cycling buildings aggressively: The next frontier in HVAC control. IPSN 2011: 246-257

Rajesh K. Gupta, Vincent John Mooney (Eds.): Proceedings of the 14th International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2011, part of the Seventh Embedded Systems Week, ESWeek 2011, Taipei, Taiwan, October 9-14, 2011. ACM 2011, isbn 978-1-4503-0713-0

Muhammad Abdullah Adnan, Yan Ma, Ryo Sugihara, Rajesh Gupta: Dynamic Deferral of Workload for Capacity Provisioning in Data Centers. CoRR abs/1109.3839 (2011)

Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta: Translation Validation of High-Level Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 29(4): 566-579 (2010)

Rajesh Gupta, Arindam Ghosh, Avinash Joshi: Multiband Hysteresis Modulation and Switching Characterization for Sliding-Mode-Controlled Cascaded Multilevel Inverter. IEEE Transactions on Industrial Electronics 57(7): 2344-2353 (2010)

Ryo Sugihara, Rajesh K. Gupta: Optimal Speed Control of Mobile Node for Data Collection in Sensor Networks. IEEE Trans. Mob. Comput. 9(1): 127-139 (2010)

Ryo Sugihara, Rajesh K. Gupta: Speed control and scheduling of data mules in sensor networks. TOSN 7(1) (2010)

Adrian M. Caulfield, Arup De, Joel Coburn, Todor I. Mollow, Rajesh K. Gupta, Steven Swanson: Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories. MICRO 2010: 385-395

Adrian M. Caulfield, Joel Coburn, Todor I. Mollov, Arup De, Ameen Akel, Jiahua He, Arun Jagatheesan, Rajesh K. Gupta, Allan Snavely, Steven Swanson: Understanding the Impact of Emerging Non-Volatile Memories on High-Performance, IO-Intensive Computing. SC 2010: 1-11

Almir Mutapcic, Stephen P. Boyd, Srinivasan Murali, David Atienza, Giovanni De Micheli, Rajesh Gupta: Processor Speed Control With Thermal Constraints. IEEE Trans. on Circuits and Systems 56-I(9): 1994-2008 (2009)

Rajesh Gupta, Arindam Ghosh, Avinash Joshi: Characteristic Analysis for Multisampled Digital Implementation of Fixed-Switching-Frequency Closed-Loop Modulation of Voltage-Source Inverter. IEEE Transactions on Industrial Electronics 56(7): 2382-2392 (2009)

Zhong-Yi Jin, Curt Schurgers, Rajesh K. Gupta: A gateway node with duty-cycled radio and processing subsystems for wireless sensor networks. ACM Trans. Design Autom. Electr. Syst. 14(1) (2009)

Zhong-Yi Jin, Rajesh Gupta: LazySync: A New Synchronization Scheme for Distributed Simulation of Sensor Networks. DCOSS 2009: 103-116

Ryo Sugihara, Rajesh K. Gupta: Optimizing Energy-Latency Trade-Off in Sensor Networks with Controlled Mobility. INFOCOM 2009: 2566-2570

Zhong-Yi Jin, Rajesh K. Gupta: Improving the speed and scalability of distributed simulations of sensor networks. IPSN 2009: 169-180

Yuvraj Agarwal, Steve Hodges, Ranveer Chandra, James Scott, Paramvir Bahl, Rajesh Gupta: Somniloquy: Augmenting Network Interfaces to Reduce PC Energy Usage. NSDI 2009: 365-380

Patrick Verkaik, Yuvraj Agarwal, Rajesh Gupta, Alex C. Snoeren: Softspeak: Making VoIP Play Well in Existing 802.11 Deployments. NSDI 2009: 409-422

Rajesh Gupta, Arvind, Gérard Berry, Forrest Brewer: Advances in ESL Design. IEEE Design & Test of Computers 25(6): 520-526 (2008)

Rajesh Gupta, Arindam Ghosh, Avinash Joshi: Switching Characterization of Cascaded Multilevel-Inverter-Controlled Systems. IEEE Transactions on Industrial Electronics 55(3): 1047-1058 (2008)

Ryo Sugihara, Rajesh K. Gupta: Programming models for sensor networks: A survey. TOSN 4(2) (2008)

Sudipta Kundu, Sorin Lerner, Rajesh Gupta: Validating High-Level Synthesis. CAV 2008: 459-472

Sudipta Kundu, Malay K. Ganai, Rajesh Gupta: Partial order reduction for scalable testing of systemC TLM designs. DAC 2008: 936-941

Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen P. Boyd, Luca Benini, Giovanni De Micheli: Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization. DATE 2008: 110-115

Zhong-Yi Jin, Rajesh Gupta: Improved Distributed Simulation of Sensor Networks Based on Sensor Node Sleep Time. DCOSS 2008: 204-218

Ryo Sugihara, Rajesh K. Gupta: Improving the Data Delivery Latency in Sensor Networks with Controlled Mobility. DCOSS 2008: 386-399

Yuvraj Agarwal, Trevor Pering, Roy Want, Rajesh Gupta: SwitchR: Reducing system power consumption in a multi-client, multi-radio environment. ISWC 2008: 99-102

Marcelo Lubaszewski, Michel Renovell, Rajesh K. Gupta (Eds.): Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008. ACM 2008, isbn 978-1-60558-231-3

Sandy Irani, Sandeep K. Shukla, Rajesh Gupta: Algorithms for power savings. ACM Transactions on Algorithms 3(4) (2007)

Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen P. Boyd, Giovanni De Micheli: Temperature-aware processor frequency assignment for MPSoCs using convex optimization. CODES+ISSS 2007: 111-116

Dohyung Kim, Soonhoi Ha, Rajesh Gupta: CATS: cycle accurate transaction-driven simulation with multiple processor simulators. DATE 2007: 749-754

Frederic Doucet, R. K. Shyamasundar, Ingolf H. Krüger, Saurabh Joshi, Rajesh K. Gupta: Reactivity in SystemC Transaction-Level Models. Haifa Verification Conference 2007: 34-50

Sudipta Kundu, Sorin Lerner, Rajesh Gupta: Automated refinement checking of concurrent systems. ICCAD 2007: 318-325

Yuvraj Agarwal, Ranveer Chandra, Alec Wolman, Paramvir Bahl, Kevin Chin, Rajesh K. Gupta: Wireless wakeups revisited: energy management for voip over wi-fi smartphones. MobiSys 2007: 179-191

Zhong-Yi Jin, Curt Schurgers, Rajesh K. Gupta: An Embedded Platform with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor Networks. SAMOS 2007: 421-430

Frederic Doucet, Massimiliano Menarini, Ingolf H. Krüger, Rajesh K. Gupta, Jean-Pierre Talpin: A Verification Approach for GALS Integration of Synchronous Components. Electr. Notes Theor. Comput. Sci. 146(2): 105-131 (2006)

Ravindra Jejurikar, Rajesh Gupta: Optimized Slowdown in Real-Time Task Systems. IEEE Trans. Computers 55(12): 1588-1598 (2006)

Ravindra Jejurikar, Rajesh K. Gupta: Energy-aware task scheduling with task synchronization for embedded real-time systems. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1024-1037 (2006)

Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil D. Dutt, Rajesh K. Gupta: Energy efficient watermarking on mobile devices using proxy-based partitioning. IEEE Trans. VLSI Syst. 14(6): 625-636 (2006)

Chalermek Intanagonwiwat, Rajesh K. Gupta, Amin Vahdat: Declarative Resource Naming for Macroprogramming Wireless Networks of Embedded Systems. ALGOSENSORS 2006: 192-199

Jeffrey Namkung, Dohyung Kim, Rajesh K. Gupta, Igor Kozintsev, Jean-Yves Bouguet, Carole Dulong: Phase guided sampling for efficient parallel application simulation. CODES+ISSS 2006: 187-192

Dohyung Kim, Soonhoi Ha, Rajesh Gupta: Parallel co-simulation using virtual synchronization with redundant host execution. DATE 2006: 1151-1156

Frederic Doucet, Ingolf Krüger, Rajesh K. Gupta, R. K. Shyamasundar: Compositional interaction specifications for SystemC. MEMOCODE 2006: 201

Trevor Pering, Yuvraj Agarwal, Rajesh K. Gupta, Roy Want: CoolSpots: reducing the power consumption of wireless mobile devices with multiple radio interfaces. MobiSys 2006: 220-232

Rajesh K. Gupta: Global competitiveness, outsourcing, and education in the semiconductor industry. IEEE Design & Test of Computers 22(1): 5-6 (2005)

Rajesh K. Gupta: FPGA-enabled computing architectures. IEEE Design & Test of Computers 22(2): 81 (2005)

Rajesh K. Gupta: The other face of design for manufacturability. IEEE Design & Test of Computers 22(3): 193 (2005)

Rajesh K. Gupta: Nanotechnology: Where science of the small meets math of the large. IEEE Design & Test of Computers 22(4): 289, 294 (2005)

Rajesh K. Gupta: On-chip networks. IEEE Design & Test of Computers 22(5): 393 (2005)

Rajesh K. Gupta: Going 3D: Silicon and D&T. IEEE Design & Test of Computers 22(6): 493-494 (2005)

Gethin Norman, David Parker, Marta Z. Kwiatkowska, Sandeep K. Shukla, Rajesh Gupta: Using probabilistic model checking for dynamic power management. Formal Asp. Comput. 17(2): 160-176 (2005)

Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla, Rajesh Gupta: A Compositional Behavioral Modeling Framework for Embedded System Design and Conformance Checking. International Journal of Parallel Programming 33(6): 613-643 (2005)

Paolo D'Alberto, Alexandru Nicolau, Alexander V. Veidenbaum, Rajesh K. Gupta: Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache. IEEE Trans. Computers 54(2): 185-197 (2005)

Vijay Raghunathan, Cristiano Pereira, Mani B. Srivastava, Rajesh K. Gupta: Energy-aware wireless systems with adaptive power-fidelity tradeoffs. IEEE Trans. VLSI Syst. 13(2): 211-225 (2005)

Sandy Irani, Gaurav Singh, Sandeep K. Shukla, Rajesh K. Gupta: An overview of the competitive and adversarial approaches to designing dynamic power management strategies. IEEE Trans. VLSI Syst. 13(12): 1349-1361 (2005)

Yuvraj Agarwal, Curt Schurgers, Rajesh Gupta: Dynamic power management using on demand paging for networked embedded systems. ASP-DAC 2005: 755-759

Cristiano Pereira, Jeremy Lau, Brad Calder, Rajesh K. Gupta: Dynamic phase analysis for cycle-close trace generation. CODES+ISSS 2005: 321-326

Ravindra Jejurikar, Rajesh K. Gupta: Dynamic slack reclamation with procrastination scheduling in real-time embedded systems. DAC 2005: 111-116

Ravindra Jejurikar, Rajesh K. Gupta: Energy Aware Non-Preemptive Scheduling for Hard Real-Time Systems. ECRTS 2005: 21-30

Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil Dutt, Rajesh Gupta: Energy Analysis of Multimedia Watermarking on Mobile Handheld Devices. ESTImedia 2005: 33-38

Shivajit Mohapatra, Radu Cornea, Hyunok Oh, Kyoungwoo Lee, Minyoung Kim, Nikil D. Dutt, Rajesh Gupta, Alexandru Nicolau, Sandeep K. Shukla, Nalini Venkatasubramanian: A Cross-Layer Approach for Power-Performance Optimization in Distributed Mobile Systems. IPDPS 2005

Nicolae Savoiu, Sandeep K. Shukla, Rajesh K. Gupta: Improving SystemC simulation through Petri net reductions. MEMOCODE 2005: 131-140

Luca Benini, Sandeep K. Shukla, Rajesh K. Gupta: Architectural, System Level and Protocol Level Techniques for Power Optimization for Networked Embedded Systems. VLSI Design 2005: 18-

Hiren D. Patel, Sumit Gupta, Sandeep K. Shukla, Rajesh Gupta: An Introductory Survey of Networked Embedded Systems. The Industrial Information Technology Handbook 2005: 0-

Rajesh Gupta: From the Editor in Chief: Predictability in Design and Manufacturing. IEEE Design & Test of Computers 21(1): 1- (2004)

Rajesh Gupta: From the EIC: Past successes, future challenges. IEEE Design & Test of Computers 21(2): 77-78 (2004)

Rajesh Gupta: From the EIC: The next EDA challenge - Design for manufacturability. IEEE Design & Test of Computers 21(3): 169- (2004)

Rajesh Gupta: Silicon for embedded multimedia processing. IEEE Design & Test of Computers 21(5): 345- (2004)

Rajesh K. Gupta: Verification synergies. IEEE Design & Test of Computers 21(6): 457 (2004)

Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla, Frederic Doucet, Rajesh K. Gupta: Formal Refinement Checking in a System-level Design Methodology. Fundam. Inform. 62(2): 243-273 (2004)

Rajesh Gupta, Pramod R. Bhave: Comments on the paper 'Redundancy model for water distribution systems' by P. Kalungi and T.T. Tanyimboh. Rel. Eng. & Sys. Safety 86(3): 331-333 (2004)

Sumit Gupta, Nicolae Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: Using global code motions to improve the quality of results for high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 302-312 (2004)

Rajesh Gupta: Guest editorial: Special issue on networked embedded systems. ACM Trans. Embedded Comput. Syst. 3(1): 1-2 (2004)

Sumit Gupta, Rajesh K. Gupta, Nikil D. Dutt, Alexandru Nicolau: Coordinated parallelizing compiler optimizations and high-level synthesis. ACM Trans. Design Autom. Electr. Syst. 9(4): 441-470 (2004)

Jean-Pierre Talpin, David Berner, Sandeep K. Shukla, Paul Le Guernic, Abdoulaye Gamatié, Rajesh Gupta: A Behavioral Type Inference System for Compositional System-on-Chip Design. ACSD 2004: 47-56

Rajesh Gupta, R. K. Shyamasundar: Reactive Framework for Resource Aware Distributed Computing. ASIAN 2004: 452-467

Ravindra Jejurikar, Cristiano Pereira, Rajesh K. Gupta: Leakage aware dynamic voltage scaling for real-time embedded systems. DAC 2004: 275-280

Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil Dutt, Rajesh Gupta: Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices. DAC 2004: 556-561

Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alexandru Nicolau: Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow. DATE 2004: 114-121

Nikhil Bansal, Sumit Gupta, Nikil Dutt, Alexandru Nicolau, Rajesh Gupta: Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures. DATE 2004: 474-479

Hans Van Antwerpen, Nikil D. Dutt, Rajesh K. Gupta, Shivajit Mohapatra, Cristiano Pereira, Nalini Venkatasubramanian, Ralph von Vignau: Energy-Aware System Design for Wireless Multimedia. DATE 2004: 1124-1131

Ravindra Jejurikar, Rajesh K. Gupta: Optimized Slowdown in Real-Time Task Systems. ECRTS 2004: 155-164

Nikhil Bansal, Sumit Gupta, Nikil D. Dutt, Alexandru Nicolau, Rajesh K. Gupta: Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures. FPL 2004: 891-899

Ravindra Jejurikar, Rajesh K. Gupta: Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems. ISLPED 2004: 78-81

Ravindra Jejurikar, Rajesh K. Gupta: Procrastination scheduling in fixed priority real-time systems. LCTES 2004: 57-66

Rajesh K. Gupta: Driving Research in System-Chip Design Technology. IEEE Computer 36(7): 95-97 (2003)

Rajesh Gupta: From the Editor in Chief: Twenty years! IEEE Design & Test of Computers 20(1): 1- (2003)

Rajesh Gupta: From the Editor in Chief: Full Circle? IEEE Design & Test of Computers 20(2): 1- (2003)

Rajesh Gupta: From the Editor in Chief: A "Powerful" Issue! IEEE Design & Test of Computers 20(3): 1- (2003)

Rajesh Gupta: From the Editor in Chief: Addressing Problems of the Large. IEEE Design & Test of Computers 20(4): 3- (2003)

Rajesh Gupta: At-Speed Testing: A Shared Red Brick between Design and Test. IEEE Design & Test of Computers 20(5): 1- (2003)

Rajesh Gupta: From the EIC: The changing face of IC design and its industry. IEEE Design & Test of Computers 20(6): 1- (2003)

Frederic Doucet, Sandeep K. Shukla, Masato Otsuka, Rajesh K. Gupta: BALBOA: a component-based design environment for system models. IEEE Trans. on CAD of Integrated Circuits and Systems 22(12): 1597-1612 (2003)

Sandy Irani, Sandeep K. Shukla, Rajesh K. Gupta: Online strategies for dynamic power management in systems with multiple power-saving states. ACM Trans. Embedded Comput. Syst. 2(3): 325-346 (2003)

Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla, Rajesh K. Gupta, Frederic Doucet: Polychrony for Formal Refinement-Checking in a System-Level Design Methodology. ACSD 2003: 9-19

Frederic Doucet, Sandeep K. Shukla, Rajesh K. Gupta: Typing abstractions and management in a component framework. ASP-DAC 2003: 115-122

Rajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi: Formal verification - prove it or pitch it. DAC 2003: 710-711

Vijay Raghunathan, Mani B. Srivastava, Rajesh K. Gupta: A survey of techniques for energy efficient on-chip communication. DAC 2003: 900-905

Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs. DATE 2003: 10270-10275

Frederic Doucet, Sandeep K. Shukla, Rajesh K. Gupta: Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated. DATE 2003: 10382-10387

Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla, Rajesh K. Gupta, Frederic Doucet: Polychrony for Refinement-Based Design. DATE 2003: 11172-11173

Rajesh K. Gupta, Sandy Irani, Sandeep K. Shukla: Formal Methods for Dynamic Power Management. ICCAD 2003: 874-882

Manev Luthra, Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: Interface Synthesis using Memory Mapping for an FPGA Platform. ICCD 2003: 140-145

Radu Cornea, Nikil D. Dutt, Rajesh K. Gupta, Ingolf Krüger, Alexandru Nicolau, Douglas C. Schmidt, Sandeep K. Shukla: FORGE: A Framework for Optimization of Distributed Embedded Systems Software. IPDPS 2003: 208

Rajesh K. Gupta, Sandeep K. Shukla: Should the space of implementation possibilities be determined by the abilities of high-level synthesis and validation? MEMOCODE 2003: 277-

Sandy Irani, Sandeep K. Shukla, Rajesh K. Gupta: Algorithms for power savings. SODA 2003: 37-46

Sandeep K. Shukla, Jean-Pierre Talpin, Stephen A. Edwards, Rajesh K. Gupta: High Level Modeling and Validation Methodologies for Embedded Systems: Bridging the Productivity Gap. VLSI Design 2003: 9-14

Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations. VLSI Design 2003: 461-466

Rajesh Gupta, Yukihiro Nakamura, Alex Orailoglu, Pai H. Chou (Eds.): Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003. ACM 2003, isbn 1-58113-742-7

Rajesh Gupta: Sustaining an Industry Obsession. IEEE Design & Test of Computers 19(5): 1- (2002)

Rajesh Gupta: EIC Message: The Neglected Community. IEEE Design & Test of Computers 19(6): 3- (2002)

Amit Chowdhary, Rajesh K. Gupta: A Methodology for Synthesis of Data Path Circuitse. IEEE Design & Test of Computers 19(6): 90-100 (2002)

Dinesh Ramanathan, Sandy Irani, Rajesh K. Gupta: An analysis of system level power management algorithms and theireffects on latency. IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 291-305 (2002)

Ki-Seok Chung, Rajesh K. Gupta, Taewhan Kim, C. L. Liu: Synthesis and Optimization of Combinational Interface Circuits. VLSI Signal Processing 31(3): 243-261 (2002)

Ravindra Jejurikar, Rajesh K. Gupta: Energy aware task scheduling with task synchronization for embedded real time systems. CASES 2002: 164-169

Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem: Coordinated transformations for high-level synthesis of high performance microprocessor blocks. DAC 2002: 898-903

Sandy Irani, Rajesh K. Gupta, Sandeep K. Shukla: Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings States. DATE 2002: 117-123

Ana Azevedo, Ilya Issenin, Radu Cornea, Rajesh Gupta, Nikil D. Dutt, Alexander V. Veidenbaum, Alexandru Nicolau: Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints. DATE 2002: 168-175

Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau: Power Savings in Embedded Processors through Decode Filer Cache. DATE 2002: 443-448

Frederic Doucet, Sandeep K. Shukla, Rajesh K. Gupta, Masato Otsuka: An Environment for Dynamic Component Composition for Efficient Co-Design . DATE 2002: 736-743

Nick Savoiu, Sandeep K. Shukla, Rajesh K. Gupta: Automated Concurrency Re-Assignment in High Level System Models for Efficient System-Level Simulation. DATE 2002: 875-881

Sandeep K. Shukla, Frederic Doucet, Rajesh K. Gupta: Structured Component Composition Frameworks for Embedded System Design. HiPC 2002: 663-678

Gethin Norman, David Parker, Marta Z. Kwiatkowska, Sandeep K. Shukla, Rajesh K. Gupta: Formal analysis and validation of continuous-time Markov chain based system level power management strategies. HLDVT 2002: 45-50

Mohammad Reza Mousavi, Giovanni Russello, Michel R. V. Chaudron, Michel A. Reniers, Twan Basten, Angelo Corsaro, Sandeep K. Shukla, Rajesh K. Gupta, Douglas C. Schmidt: Using Aspect-GAMMA in the design of embedded systems. HLDVT 2002: 69-74

Shailesh Ramamurthy, Sanjeev Madhavankutty, V. Meena, Rajesh Gupta: JPEG-2000 on an advanced architecture, multiple execution unit DSP. ISCAS (4) 2002: 325-328

Weiyu Tang, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta: Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption. ISHPC 2002: 120-132

Rajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu: Efficient Simulation of Synthesis-Oriented System Level Designs. ISSS 2002: 168-173

Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Nick Savoiu, Mehrdad Reshadi, Sumit Gupta: Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis. ISSS 2002: 261-266

Nick Savoiu, Sandeep K. Shukla, Rajesh K. Gupta: Concurrency in System Level Design: Conflict Between Simulation and Synthesis Goals. IWLS 2002: 407-411

Luciano Lavagno, Sujit Dey, Rajesh K. Gupta: Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract). VLSI Design 2002: 21-23

Jörg Henkel, Xiaobo Sharon Hu, Rajesh Gupta, Sri Parameswaran (Eds.): Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, Estes Park, Colorado, USA, May 6-8, 2002. ACM 2002, isbn 1-58113-542-4

Rajesh K. Gupta, Shishpal Rawat, Ingrid Verbauwhede, Gérard Berry, Ramesh Chandra, Daniel Gajski, Kris Konigsfeld, Patrick Schaumont: Panel: The Next HDL: If C++ is the Answer, What was the Question? DAC 2001: 71-72

Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: Speculation Techniques for High Level Synthesis of Control Intensive Designs. DAC 2001: 269-272

Sandeep K. Shukla, Rajesh K. Gupta: A model checking approach to evaluating system level dynamic power management policies for embedded systems. HLDVT 2001: 53-57

Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau: Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures. ICCD 2001: 68-75

Frederic Doucet, Rajesh K. Gupta, Masato Otsuka, Patrick Schaumont, Sandeep K. Shukla: Interoperability as a design issue in C++ based modeling environments. ISSS 2001: 87-92

Wolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R. Gao, Rajesh K. Gupta, Preeti Ranjan Panda: New design paradigms. ISSS 2001: 94

Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: Conditional speculation and its effects on performance and area for high-level snthesis. ISSS 2001: 171-176

Jian Li, Rajesh K. Gupta: HDL presynthesis optimizations using a tabular model. IEEE Trans. VLSI Syst. 8(4): 369-378 (2000)

Dinesh Ramanathan, Ravindra Jejurikar, Rajesh K. Gupta: Timing driven co-design of networked embedded systems. ASP-DAC 2000: 117-122

Prashant Arora, Rajesh K. Gupta: Design and implementation of a hierarchical exception handling extension to systemC. CASES 2000: 80-84

Sumit Gupta, Rajesh K. Gupta, Miguel Miranda, Francky Catthoor: Analysis of High-Level Address Code Transformations for Programmable Processors. DATE 2000: 9-13

Dinesh Ramanathan, Rajesh K. Gupta: System Level Online Power Management Algorithms. DATE 2000: 606-611

Dinesh Ramanathan, Sandy Irani, Rajesh K. Gupta: Latency Effects of System Level Power Management Algorithms. ICCAD 2000: 350-356

Dinesh Ramanathan, Rajesh K. Gupta, Raymond Roth: Interfacing Hardware and Software Using C++ Class Libraries. ICCD 2000: 445-

Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta: Compiler-Directed Cache Line Size Adaptivity. Intelligent Memory Systems 2000: 183-187

Xiaomei Ji, Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta: Compiler-Directed Cache Assist Adaptivity. ISHPC 2000: 88-104

Vivek Sinha, Frederic Doucet, Chuck Siska, Rajesh K. Gupta, Stan Y. Liao, Abhijit Ghosh: YAML: A Tool for Hardware Design Visualization and Capture. ISSS 2000: 9-17

Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta: Extraction of functional regularity in datapath circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1279-1296 (1999)

Dinesh Ramanathan, Ali Dasdan, Rajesh K. Gupta: Timing-driven HW/SW codesign based on task structuring and process timing simulation. CODES 1999: 203-207

Ali Dasdan, Sandy Irani, Rajesh K. Gupta: Efficient Algorithms for Optimum Cycle Mean and Optimum Cost to Time Ratio Problems. DAC 1999: 37-42

Alexander V. Veidenbaum, Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau, Xiaomei Ji: Adapting cache line size to application behavior. International Conference on Supercomputing 1999: 145-154

Ali Dasdan, Rajesh K. Gupta: Faster maximum and minimum mean cycle algorithms for system-performance analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 889-899 (1998)

Anmol Mathur, Ali Dasdan, Rajesh K. Gupta: Rate analysis for embedded systems. ACM Trans. Design Autom. Electr. Syst. 3(3): 408-436 (1998)

Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta: A timing-driven design and validation methodology for embedded real-time systems. ACM Trans. Design Autom. Electr. Syst. 3(4): 533-553 (1998)

Jian Li, Rajesh K. Gupta: HDL code restructuring using timed decision tables. CODES 1998: 131-135

Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta: Rate Derivation and Its Applications to Reactive, Real-Time Embedded Systems. DAC 1998: 263-268

Jian Li, Rajesh K. Gupta: An Algorithm To Determine Mutually Exclusive Operations In Behavioral Descriptions. DATE 1998: 457-463

Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta: A general approach for regularity extraction in datapath circuits. ICCAD 1998: 332-339

Zhang Yang, Rajesh K. Gupta: A Case Analysis of System Partitioning and Its Relationship To High-Level Synthesis Tasks. VLSI Design 1998: 442-448

Rajesh K. Gupta: Editorial: Special Issue on Hardware/Software Partitioning. Design Autom. for Emb. Sys. 2(2): 123-124 (1997)

Rajesh K. Gupta, Stan Y. Liao: Using a Programming Language for Digital System Design. IEEE Design & Test of Computers 14(2): 72-80 (1997)

Yervant Zorian, Rajesh K. Gupta: Design and Test of Core-Based Systems on Chips. IEEE Design & Test of Computers 14(4): 14- (1997)

Rajesh K. Gupta, Yervant Zorian: Introducing Core-Based System Design. IEEE Design & Test of Computers 14(4): 15-25 (1997)

Rajesh K. Gupta, Giovanni De Micheli: Constrained software synthesis for embedded applications. Journal of Systems Architecture 43(8): 557-586 (1997)

Venkatram Krishnaswamy, Rajesh Gupta, Prithviraj Banerjee: Implications of VHDL timing models on simulation and software synthesis. Journal of Systems Architecture 44(1): 23-36 (1997)

Rajesh K. Gupta, Giovanni De Micheli: Specification and analysis of timing constraints for embedded systems. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 240-256 (1997)

Venkatram Krishnaswamy, Rajesh Gupta, Prithviraj Banerjee: A procedure for software synthesis from VHDL models. ASP-DAC 1997: 593-598

Stan Y. Liao, Steven W. K. Tjiang, Rajesh K. Gupta: An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design Environment. DAC 1997: 70-75

Jian Li, Rajesh K. Gupta: Limited Exception Modeling and Its Use in Presynthesis Optimizations. DAC 1997: 341-346

Samir Agrawal, Rajesh K. Gupta: Data-Flow Assisted Behavioral Partitioning for Embedded Systems. DAC 1997: 709-712

Ali Dasdan, Anmol Mathur, Rajesh K. Gupta: RATAN: A tool for rate analysis and rate constraint debugging for embedded systems. ED&TC 1997: 2-6

Rajesh K. Gupta, Mani B. Srivastava: Design technology for building wireless systems (tutorial). ICCAD 1997

Jian Li, Rajesh K. Gupta: Decomposition of timed decision tables and its use in presynthesis optimizations. ICCAD 1997: 22-27

Xingbin Zhang, Ali Dasdan, Martin Schulz, Rajesh K. Gupta, Andrew A. Chien: Architectural Adaptation for Application-Specific Locality Optimization. ICCD 1997: 150-156

Rajesh K. Gupta, Giovanni De Micheli: A co-synthesis approach to embedded system design automation. Design Autom. for Emb. Sys. 1(1-2): 69-120 (1996)

John Y. Sayah, Rajesh Gupta, Deepak D. Sherlekar, Philip S. Honsinger, Jitendra M. Apte, S. Wayne Bollinger, Hai Hsia Chen, Sumit DasGupta, Edward P. Hsieh, Andrew D. Huber, Edward J. Hughes, Zahi M. Kurzum, Vasant B. Rao, Thepthai Tabtieng, Vigen Valijan, David Y. Yang: Design planning for high-performance ASICs. IBM Journal of Research and Development 40(4): 431-452 (1996)

Jian Li, Rajesh K. Gupta: HDL Optimization Using Timed Decision Tables. DAC 1996: 51-54

Rajesh K. Gupta: Analysis of Operation Delay and Execution Rate Constraints for Embedded Systems. DAC 1996: 601-604

Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu: An algorithm for synthesis of system-level interface circuits. ICCAD 1996: 442-447

Rajesh K. Gupta, Daniel Gajski, Randy Allen, Yatin Trivedi: Opportunities and pitfalls in HDL-based system design. ICCD 1996: 56-

Rajesh Gupta: Hardware Software Co-Design of Embedded Systems. VLSI Design 1996: 3

Rajesh Gupta, Melvin A. Breuer: Partial scan design of register-transfer level circuits. J. Electronic Testing 7(1-2): 25-46 (1995)

Vinod Narayananan, David LaPotin, Rajesh K. Gupta, Gopalakrishnan Vijayan: PEPPER - a timing driven early floorplanner. ICCD 1995: 230-235

Rajesh K. Gupta, Claudionor José Nunes Coelho Jr., Giovanni De Micheli: Program Implementation Schemes for Hardware-Software Systems. IEEE Computer 27(1): 48-55 (1994)

Rajesh K. Gupta, Giovanni De Micheli: Constrained software generation for hardware-software systems. CODES 1994: 56-63

Rajesh K. Gupta, Giovanni De Micheli: Hardware-Software Cosynthesis for Digital Systems. IEEE Design & Test of Computers 10(3): 29-41 (1993)

Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer: Optimal Configuring of Multiple Scan Chains. IEEE Trans. Computers 42(9): 1121-1131 (1993)

Rajesh K. Gupta, Claudionor José Nunes Coelho Jr., Giovanni De Micheli: Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components. DAC 1992: 225-230

Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer: Configuring multiple scan chains for minimum test time. ICCAD 1992: 4-8

Rajesh Gupta, Melvin A. Breuer: Ordering Storage Elements in a Single Scan Chain. ICCAD 1991: 408-411

Rajesh Gupta, Rajiv Gupta, Melvin A. Breuer: The BALLAST Methodology for Structured Partial Scan Design. IEEE Trans. Computers 39(4): 538-544 (1990)

Rajesh K. Gupta, Giovanni De Micheli: Partitioning of Functional Models of Synchronous Digital Systems. ICCAD 1990: 216-219

Rajiv Gupta, Wesley H. Cheng, Rajesh Gupta, Ido Hardonag, Melvin A. Breuer: An Object-Oriented VLSI CAD Framework: A Case Study in Rapid Prototyping. IEEE Computer 22(5): 28-37 (1989)

Rajesh Gupta, Melvin A. Breuer: BALLAST: a methodology for partial scan design. FTCS 1989: 118-125