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Renaud Gillon

2010 – today

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2012
[j4]
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  dblp key:
  - journals/mj/RhayemBBBHPDGWT12
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J. Rhayem, B. Besbes, R. Blecic, Sergey Bychikhin, G. Haberfehlner, Dionyz Pogany, B. Desoete, Renaud Gillon, A. Wieers, Marnix Tack: Electro-thermal characterization and simulation of integrated multi-trenched XtreMOS^TM power devices. Microelectronics Journal 43(9): 618-623 (2012)
[j3]
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  dblp key:
  - journals/mr/IvankovicVVBGBV12
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Andrej Ivankovic, Kris Vanstreels, Daniel Vanderstraeten, Guy Brizar, Renaud Gillon, Eddy Blansaer, Bart Vandevelde: Comparison of experimental methods for the extraction of the elastic modulus of molding compounds used in IC packaging. Microelectronics Reliability 52(11): 2677-2684 (2012)
2010
[j2]
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  dblp key:
  - journals/mr/BychikhinHRVGP10
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Sergey Bychikhin, G. Haberfehlner, J. Rhayem, Daniel Vanderstraeten, Renaud Gillon, Dionyz Pogany: Investigation of smart power DMOS devices under repetitive stress conditions using transient thermal mapping and numerical simulation. Microelectronics Reliability 50(9-11): 1427-1430 (2010)

2000 – 2009

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What is the meaning of the colors in the publication list?

2009
[c3]
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  dblp key:
  - conf/icecsys/MandicVGCB09
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Tvrtko Mandic, Filip Vanhee, Renaud Gillon, Johan Catrysse, Adrijan Baric: Equivalent circuit model of the TEM cell electric and magnetic field coupling to microstrip lines. ICECS 2009: 247-250
2007
[c2]
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  dblp key:
  - conf/vlsid/ChauhanKGBDI07
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Yogesh Singh Chauhan, François Krummenacher, Renaud Gillon, Benoit Bakeroot, Michel J. Declercq, Adrian M. Ionescu: A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling. VLSI Design 2007: 177-182
2006
[c1]
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  - conf/isqed/ChauhanAKGB06
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Yogesh Singh Chauhan, C. Anghel, François Krummenacher, Renaud Gillon, A. Baguenier: A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor. ISQED 2006: 109-114
2001
[j1]
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  dblp key:
  - journals/mr/NingSVGTR01
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Zhenqiu Ning, Yuri Sneyders, Wim Vanderbauwhede, Renaud Gillon, Marnix Tack, Paul Raes: A compact test structure for characterisation of leakage currents in sub-micron CMOS technologies. Microelectronics Reliability 41(12): 1939-1945 (2001)