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Minoru Fujishima
2010 – today
- 2013
[j12]Ryuichi Fujimoto, Mizuki Motoyoshi, Kyoya Takano, Minoru Fujishima: A 120 GHz/140 GHz Dual-Channel OOK Receiver Using 65 nm CMOS Technology. IEICE Transactions 96-A(2): 486-493 (2013)- [c12]Kyoya Takano, Ryuichi Fujimoto, Mizuki Motoyoshi, Kosuke Katayama, Minoru Fujishima: 14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers. RWS 2013: 235-237
- 2012
- [j11]Kosuke Katayama, Mizuki Motoyoshi, Kyoya Takano, Ryuichi Fujimoto, Minoru Fujishima: Bias-Voltage-Dependent Subcircuit Model for Millimeter-Wave CMOS Circuit. IEICE Transactions 95-C(6): 1077-1085 (2012)
- [j10]Ryuichi Fujimoto, Mizuki Motoyoshi, Kyoya Takano, Uroschanit Yodprasit, Minoru Fujishima: A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology. IEICE Transactions 95-C(7): 1154-1162 (2012)
- [c11]Naoko Ono, Mizuki Motoyoshi, Kosuke Katayama, Minoru Fujishima: 125 GHz CMOS oscillator controlled by p-type bulk voltage. RWS 2012: 215-218
- 2011
- [j9]Koji Kai, Minoru Fujishima: Prospective Silicon Applications and Technologies in 2025. IEICE Transactions 94-C(4): 386-393 (2011)
- [j8]Ryuichi Fujimoto, Kyoya Takano, Mizuki Motoyoshi, Uroschanit Yodprasit, Minoru Fujishima: Device Modeling Techniques for High-Frequency Circuits Design Using Bond-Based Design at over 100 GHz. IEICE Transactions 94-C(4): 589-597 (2011)
- [j7]Kyoya Takano, Ryuichi Fujimoto, Kosuke Katayama, Mizuki Motoyoshi, Minoru Fujishima: Analysis of De-Embedding Error Cancellation in Cascade Circuit Design. IEICE Transactions 94-C(10): 1641-1649 (2011)
2000 – 2009
- 2009
- [j6]Yasuo Manzawa, Masato Sasaki, Minoru Fujishima: High-Attenuation Power Line for Wideband Decoupling. IEICE Transactions 92-C(6): 792-797 (2009)
- [c10]Ahmet Öncü, Minoru Fujishima: Low-power CMOS transceiver circuits for 60GHz band millimeter-wave impulse radio. ASP-DAC 2009: 99-100
- 2008
- [j5]Kyoya Takano, Mizuki Motoyoshi, Minoru Fujishima: 4.8 GHz CMOS Frequency Multiplier Using Subharmonic Pulse-Injection Locking for Spurious Suppression. IEICE Transactions 91-C(11): 1738-1743 (2008)
- 2007
- [j4]Ivan Chee Hong Lai, Minoru Fujishima: An Integrated Low-Power CMOS Up-Conversion Mixer Using New Stacked Marchand Baluns. IEICE Transactions 90-C(4): 823-828 (2007)
- [j3]Koji Ishibashi, Ivan Chee Hong Lai, Kyoya Takano, Minoru Fujishima: A Scalable Model of Shielded Capacitors Using Mirror Image Effects. IEICE Transactions 90-C(12): 2237-2244 (2007)
- [c9]Ahmet Öncü, B. B. M. Wasanthamala Badalawa, Tong Wang, Minoru Fujishima: 22-29GHz Ultra-Wideband CMOS Pulse Generator for Collision Avoidance Short Range Vehicular Radar Sensors. ASP-DAC 2007: 94-95
- [c8]Ivan Chee Hong Lai, Yuki Kambayashi, Minoru Fujishima: 50GHz Double-Balanced Up-Conversion Mixer Using CMOS 90nm Process. ISCAS 2007: 2542-2545
- 2006
- [j2]Ivan Chee Hong Lai, Hideyuki Tanimoto, Minoru Fujishima: Characterization of High Q Transmission Line Structure for Advanced CMOS Processes. IEICE Transactions 89-C(12): 1872-1879 (2006)
- 2004
- [c7]Ken Yamamoto, Takayasu Norimatsu, Minoru Fujishima: High-speed and wide-tuning-range LC frequency dividers. ISCAS (4) 2004: 361-364
- 2003
- [c6]
- [c5]Ken Yamamoto, Minoru Fujishima, Koichiro Hoh: Optimization of shield structures in analog integrated circuits. ISCAS (1) 2003: 753-756
- [c4]Minoru Fujishima, Kaoru Saito, M. Onouchi, Koichiro Hoh: High-speed processor for quantum-computing emulation and its applications. ISCAS (4) 2003: 884-887
- 2002
- [c3]Shin-ichi O'Uchi, Minoru Fujishima, Koichiro Hoh: An 8-qubit quantum-circuit processor. ISCAS (5) 2002: 209-212
1990 – 1999
- 1999
- [j1]Takahiro Irita, Takayuki Ogura, Minoru Fujishima, Koichiro Hoh: Microprocessor architecture utilizing redundant-binary operation. Systems and Computers in Japan 30(13): 106-115 (1999)
- 1998
- [c2]Teppei Tsujita, Takahiro Irita, Minoru Fujishima, Koichiro Hoh: Self-oscillating chaos generator using CMOS multivibrator. KES (1) 1998: 213-217
- [c1]Koichiro Hoh, Takahiro Irita, Teppei Tsujita, Minoru Fujishima: Generation of chaos with simple sets of semiconductor devices. KES (3) 1998: 250-259
Coauthor Index
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last updated on 2013-04-14 02:20 CEST by the dblp team