Gennady Feygin

Jaimin Mehta, Robert B. Staszewski, Oren Eliezer, Sameh Rezeq, Khurram Waheed, Mitch Entezari, Gennady Feygin, Sudheer Vemulapalli, Vasile Zoicas, Chih-Ming Hung, Nathen Barton, Imran Bashir, Kenneth Maggio, Michel Frechette, Meng-Chang Lee, John L. Wallberg, Patrick Cruise, Naveen K. Yanduru: A 0.8mm² all-digital SAW-less polar transmitter in 65nm EDGE SoC. ISSCC 2010: 58-59

Gennady Feygin, P. Glenn Gulak, Paul Chow: Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding. Inf. Process. Manage. 30(6): 805-816 (1994)

Gennady Feygin, P. Glenn Gulak, Paul Chow: Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression. Data Compression Conference 1994: 254-263

Gennady Feygin, Patrick Glenn Gulak: Architectural tradeoffs for survivor sequence memory management in Viterbi decoders. IEEE Transactions on Communications 41(3): 425-429 (1993)

Gennady Feygin, Patrick Glenn Gulak, Paul Chow: A multiprocessor architecture for Viterbi decoders with linear speedup. IEEE Transactions on Signal Processing 41(9): 2907-2917 (1993)

Gennady Feygin, P. Glenn Gulak, Paul Chow: Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding. Data Compression Conference 1993: 118-127

Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton: A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. ISCAS 1993: 1945-1948