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Yoav Etsion
2010 – today
- 2013
[c17]Fahimeh Yazdanpanah, Daniel Jiménez-González, Carlos Alvarez-Martinez, Yoav Etsion, Rosa M. Badia: Analysis of the Task Superscalar Architecture Hardware Design. ICCS 2013: 339-348- 2012
- [j6]Alejandro Rico, Felipe Cabarcas, Carlos Villavieja, Milan Pavlovic, Augusto Vega, Yoav Etsion, Alex Ramírez, Mateo Valero: On the simulation of large-scale architectures using multiple application abstraction levels. TACO 8(4): 36 (2012)
- [j5]Yoav Etsion, Dror G. Feitelson: Exploiting Core Working Sets to Filter the L1 Cache with Random Sampling. IEEE Trans. Computers 61(11): 1535-1550 (2012)
- 2011
- [c16]Carlos Villavieja, Vasileios Karakostas, Lluís Vilanova, Yoav Etsion, Alex Ramírez, Avi Mendelson, Nacho Navarro, Adrián Cristal, Osman S. Unsal: DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory. PACT 2011: 340-349
- [c15]Carlos Villavieja, Yoav Etsion, Alex Ramírez, Nacho Navarro: FELI: HW/SW Support for On-Chip Distributed Shared Memory in Multicores. Euro-Par (1) 2011: 282-294
- [c14]Milan Pavlovic, Yoav Etsion, Alex Ramírez: On the memory system requirements of future scientific applications: Four case-studies. IISWC 2011: 159-170
- [c13]Alejandro Rico, Alejandro Duran, Felipe Cabarcas, Yoav Etsion, Alex Ramírez, Mateo Valero: Trace-driven simulation of multithreaded applications. ISPASS 2011: 87-96
- 2010
- [c12]Milan Pavlovic, Yoav Etsion, Alex Ramírez: Can Manycores Support the Memory Requirements of Scientific Applications? ISCA Workshops 2010: 65-76
- [c11]Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex Ramírez, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero: Task Superscalar: An Out-of-Order Task Pipeline. MICRO 2010: 89-100
- [c10]Felipe Cabarcas, Alejandro Rico, Yoav Etsion, Alex Ramírez: Interleaving granularity on high bandwidth memory architecture for CMPs. ICSAMOS 2010: 250-257
- [c9]Tal Ben-Nun, Yoav Etsion, Dror G. Feitelson: Design and implementation of a generic resource sharing virtual time dispatcher. SYSTOR 2010
2000 – 2009
- 2009
- [c8]Yoav Etsion, Tal Ben-Nun, Dror G. Feitelson: A global scheduling framework for virtualization environments. IPDPS 2009: 1-8
- 2007
- [j4]Yoav Etsion, Dror G. Feitelson: Probabilistic Prediction of Temporal Locality. Computer Architecture Letters 6(1): 17-20 (2007)
- [j3]Dror G. Feitelson, Tokunbo O. S. Adeshiyan, Daniel Balasubramanian, Yoav Etsion, Gabor Madl, Esteban Osses, Sameer Singh, Karlkim Suwanmongkol, Minhui Xie, Stephen R. Schach: Fine-grain analysis of common coupling and its application to a Linux case study. Journal of Systems and Software 80(8): 1239-1255 (2007)
- [j2]Dan Tsafrir, Yoav Etsion, Dror G. Feitelson: Backfilling Using System-Generated Predictions Rather than User Runtime Estimates. IEEE Trans. Parallel Distrib. Syst. 18(6): 789-803 (2007)
- [c7]Yoav Etsion, Dror G. Feitelson: L1 Cache Filtering Through Random Selection of Memory References. PACT 2007: 235-244
- [c6]Yoav Etsion, Dan Tsafrir, Scott Kirkpatrick, Dror G. Feitelson: Fine grained kernel logging with KLogger: experience and insights. EuroSys 2007: 259-272
- 2006
- [j1]Yoav Etsion, Dan Tsafrir, Dror G. Feitelson: Process prioritization using output production: Scheduling for multimedia. TOMCCAP 2(4): 318-342 (2006)
- 2005
- [c5]Dan Tsafrir, Yoav Etsion, Dror G. Feitelson, Scott Kirkpatrick: System noise, OS clock ticks, and fine-grained parallel applications. ICS 2005: 303-312
- [c4]
- 2004
- [c3]Yoav Etsion, Dan Tsafrir, Dror G. Feitelson: Desktop scheduling: how can we know what the user wants? NOSSDAV 2004: 110-115
- 2003
- [c2]Yoav Etsion, Dan Tsafrir, Dror G. Feitelson: Effects of clock resolution on the scheduling of interactive and soft real-time processes. SIGMETRICS 2003: 172-183
- 2001
- [c1]Yoav Etsion, Dror G. Feitelson: User-Level Communication in a System with Gang Scheduling. IPDPS 2001: 58
Coauthor Index
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last updated on 2013-06-07 00:47 CEST by the dblp team