DBLP: Kazunari Enokimoto

	2013
c6		Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang: On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression. VLSI Design 2013: 279-284
	2012
c5		Kohei Miyase, Masao Aso, Ryou Ootsuka, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Kazunari Enokimoto, Seiji Kajihara: A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits. VTS 2012: 197-202
	2011
c4		Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel: Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium 2011: 90-95
c3		Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich: SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures. ISLPED 2011: 33-38
c2		Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor: Power-aware test generation with guaranteed launch safety for at-speed scan testing. VTS 2011: 166-171
	2009
c1		Kazunari Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, H. Sone, Seiji Kajihara, Masao Aso, Hiroshi Furukawa: CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing. Asian Test Symposium 2009: 99-104

2013

Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang: On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression. VLSI Design 2013: 279-284

2012

Kohei Miyase, Masao Aso, Ryou Ootsuka, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Kazunari Enokimoto, Seiji Kajihara: A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits. VTS 2012: 197-202

2011

Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel: Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium 2011: 90-95

Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich: SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures. ISLPED 2011: 33-38

Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor: Power-aware test generation with guaranteed launch safety for at-speed scan testing. VTS 2011: 166-171

2009

Kazunari Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, H. Sone, Seiji Kajihara, Masao Aso, Hiroshi Furukawa: CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing. Asian Test Symposium 2009: 99-104

1	Masao Aso	[c5] [c1]
2	Alberto Bosio	[c4]
3	Luigi Dilillo	[c4]
4	Hiroshi Furukawa	[c5] [c1]
5	Patrick Girard	[c4] [c2]
6	Jiun-Lang Huang	[c6]
7	Seiji Kajihara	[c6] [c5] [c4] [c3] [c2] [c1]
8	Michael A. Kochte	[c3] [c2]
9	Kohei Miyase	[c6] [c5] [c4] [c3] [c2] [c1]
10	Ryou Ootsuka	[c5]
11	H. Sone	[c1]
12	Mohammad Tehranipoor	[c2]
13	Y. Uchinodan	[c4]
14	Arnaud Virazel	[c4]
15	Laung-Terng Wang	[c6]
16	Xiaoqing Wen	[c6] [c5] [c4] [c3] [c2] [c1]
17	Fangmei Wu	[c4]
18	Hans-Joachim Wunderlich	[c3]
19	Yuta Yamato	[c5] [c4] [c3] [c2] [c1]

Kazunari Enokimoto

Coauthor Index