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 | 2006 | |
|---|---|---|
| c6 |      | Harsh Dhand, Basant Kumar Dwivedi, M. Balakrishnan: New approach to architectural synthesis: incorporating QoS constraint. EMSOFT 2006: 301-310 |
| c5 | | Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrishnan, Anshul Kumar: Rapid Resource-Constrained Hardware Performance Estimation. IEEE International Workshop on Rapid System Prototyping 2006: 40-46 |
| 2004 | ||
| c4 | | Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan: Automatic synthesis of system on chip multiprocessor architectures for process networks. CODES+ISSS 2004: 60-65 |
| c3 | | Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan: Synthesis of Application Specific Multiprocessor Architectures for Process Networks. VLSI Design 2004: 780-783 |
| 2003 | ||
| c2 | | Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar: SoC Synthesis with Automatic Hardware Software Interface Generation. VLSI Design 2003: 585- |
| 2001 | ||
| c1 | | Basant Kumar Dwivedi, Jan Hoogerbrugge, Paul Stravers, M. Balakrishnan: Exploring design space of parallel realizations: MPEG-2 decoder case study. CODES 2001: 92-97 |
| 1 | M. Balakrishnan | |
| 2 | Amit Chhabra | |
| 3 | Harsh Dhand | |
| 4 | Anup Gangwar | |
| 5 | Jan Hoogerbrugge | |
| 6 | Arun Kejariwal | |
| 7 | Anshul Kumar | |
| 8 | Amarjeet Singh 0002 | |
| 9 | Paul Stravers |
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