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Rolf Drechsler
2010 – today
- 2013
[c298]Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler: Improving the mapping of reversible circuits to quantum circuits using multiple target lines. ASP-DAC 2013: 145-150- [c297]Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler: Verifying SystemC using an intermediate verification language and symbolic simulation. DAC 2013: 116
- [c296]Hoang M. Le, Daniel Große, Rolf Drechsler: Scalable fault localization for SystemC TLM designs. DATE 2013: 35-38
- [c295]Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler: Determining relevant model elements for the verification of UML/OCL specifications. DATE 2013: 1189-1192
- [c294]Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler: Towards a generic verification methodology for system models. DATE 2013: 1193-1196
- [c293]Robert Wille, Hongyan Zhang, Rolf Drechsler: Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits. ISMVL 2013: 29-34
- [c292]Laura Tague, Mathias Soeken, Shin-ichi Minato, Rolf Drechsler: Debugging of Reversible Circuits Using pDDs. ISMVL 2013: 316-321
- [c291]Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler: Exact Template Matching Using Boolean Satisfiability. ISMVL 2013: 328-333
- [c290]Mathias Soeken, Robert Wille, Eugen Kuksa, Rolf Drechsler: Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen. MBMV 2013: 99-103
- 2012
- [b10]Stephan Eggersglüß, Rolf Drechsler: High Quality Test Pattern Generation and Boolean Satisfiability. Springer 2012, ISBN 978-1-4419-9975-7, pp. I-XVIII, 1-193
- [j70]Stephan Eggersglüß, Rolf Drechsler: A Highly Fault-Efficient SAT-Based ATPG Flow. IEEE Design & Test of Computers 29(4): 63-70 (2012)
- [j69]Rolf Drechsler, Irek Ulidowski, Robert Wille: Foreword: Special Issue on Reversible Computation. Multiple-Valued Logic and Soft Computing 18(1): 1-3 (2012)
- [j68]Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler: RevKit: A Toolkit for Reversible Circuit Design. Multiple-Valued Logic and Soft Computing 18(1): 55-65 (2012)
- [j67]D. Michael Miller, Robert Wille, Rolf Drechsler: Reducing Reversible Circuit Cost by Adding Lines. Multiple-Valued Logic and Soft Computing 19(1-3): 185-201 (2012)
- [j66]Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler: Equivalence Checking of Reversible Circuits. Multiple-Valued Logic and Soft Computing 19(4): 361-378 (2012)
- [j65]Hoang M. Le, Daniel Große, Rolf Drechsler: Automatic TLM Fault Localization for SystemC. IEEE Trans. on CAD of Integrated Circuits and Systems 31(8): 1249-1262 (2012)
- [c289]Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler: Synthesis of reversible circuits with minimal lines for large functions. ASP-DAC 2012: 85-92
- [c288]Marcio F. da S. Oliveira, Christoph Kuznik, Hoang M. Le, Daniel Große, Finn Haedicke, Wolfgang Müller, Rolf Drechsler, Wolfgang Ecker, Volkan Esen: The system verification methodology for advanced TLM verification. CODES+ISSS 2012: 313-322
- [c287]Finn Haedicke, Daniel Große, Rolf Drechsler: A guiding coverage metric for formal verification. DATE 2012: 617-622
- [c286]Robert Wille, Rolf Drechsler, Christof Osewold, Alberto García Ortiz: Automatic design of low-power encoders using reversible circuit synthesis. DATE 2012: 1036-1041
- [c285]Robert Wille, Mathias Soeken, Rolf Drechsler: Debugging of inconsistent UML/OCL models. DATE 2012: 1078-1083
- [c284]Mathias Soeken, Robert Wille, Rolf Drechsler: Eliminating invariants in UML/OCL models. DATE 2012: 1142-1145
- [c283]Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler: A new SAT-based ATPG for generating highly compacted test sets. DDECS 2012: 230-235
- [c282]Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler: Coverage-Driven Stimuli Generation. DSD 2012: 525-528
- [c281]Rolf Drechsler, Mathias Soeken, Robert Wille: Formal Specification Level: Towards verification-driven design based on natural language processing. FDL 2012: 53-58
- [c280]Marc Michael, Daniel Große, Rolf Drechsler: Localizing features of ESL models for design understanding. FDL 2012: 120-125
- [c279]Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav, Rolf Drechsler: Complete and effective robustness checking by means of interpolation. FMCAD 2012: 82-90
- [c278]Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille: Completeness-Driven Development. ICGT 2012: 38-50
- [c277]Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler: Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines. ISMVL 2012: 69-74
- [c276]Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler: Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits. ISMVL 2012: 173-178
- [c275]Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler: A Synthesis Flow for Sequential Reversible Circuits. ISMVL 2012: 299-304
- [c274]Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler: Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic. ISVLSI 2012: 213-218
- [c273]Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler: CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC. MBMV 2012: 37-48
- [c272]Julia Seiter, Mathias Soeken, Robert Wille, Rolf Drechsler: Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams. RC 2012: 183-196
- [c271]Mathias Soeken, Robert Wille, Shin-ichi Minato, Rolf Drechsler: Using πDDs in the Design of Reversible Circuits. RC 2012: 197-203
- [c270]Mathias Soeken, Robert Wille, Rolf Drechsler: Assisted Behavior Driven Development Using Natural Language Processing. TOOLS (50) 2012: 269-287
- [c269]Rolf Drechsler, Robert Wille: Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology - (Invited Paper). VDAT 2012: 383-392
- [e8]Cecilia Di Chio, Alexandros Agapitos, Stefano Cagnoni, Carlos Cotta, Francisco Fernández de Vega, Gianni A. Di Caro, Rolf Drechsler, Anikó Ekárt, Anna Isabel Esparcia-Alcázar, Muddassar Farooq, William B. Langdon, Juan J. Merelo Guervós, Mike Preuss, Hendrik Richter, Sara Silva, Anabela Simões, Giovanni Squillero, Ernesto Tarantino, Andrea Tettamanzi, Julian Togelius, Neil Urquhart, Sima Uyar, Georgios N. Yannakakis (Eds.): Applications of Evolutionary Computation - EvoApplications 2012: EvoCOMNET, EvoCOMPLEX, EvoFIN, EvoGAMES, EvoHOT, EvoIASP, EvoNUM, EvoPAR, EvoRISK, EvoSTIM, and EvoSTOC, Málaga, Spain, April 11-13, 2012, Proceedings. Lecture Notes in Computer Science 7248, Springer 2012, ISBN 978-3-642-29177-7
- 2011
- [j64]Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler: Debugging reversible circuits. Integration 44(1): 51-61 (2011)
- [j63]Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler: Effective Robustness Analysis Using Bounded Model Checking Techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 30(8): 1239-1252 (2011)
- [j62]Stephan Eggersglüß, Rolf Drechsler: Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application. IEEE Trans. on CAD of Integrated Circuits and Systems 30(9): 1411-1415 (2011)
- [c268]Hongyan Zhang, Robert Wille, Rolf Drechsler: Improved Fault Diagnosis for Reversible Circuits. Asian Test Symposium 2011: 207-212
- [c267]Mathias Soeken, Robert Wille, Rolf Drechsler: Verifying dynamic aspects of UML models. DATE 2011: 1077-1082
- [c266]Robert Wille, Oliver Keszocze, Rolf Drechsler: Determining the minimal number of lines for large reversible circuits. DATE 2011: 1204-1207
- [c265]Stephan Eggersglüß, Rolf Drechsler: As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization. DATE 2011: 1291-1296
- [c264]Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler: Automatic property generation for the formal verification of bus bridges. DDECS 2011: 417-422
- [c263]Mohamed Bawadekji, Daniel Große, Rolf Drechsler: TLM protocol compliance checking at the Electronic System Level. DDECS 2011: 435-440
- [c262]Rolf Drechsler, Alexander Finder, Robert Wille: Improving ESOP-Based Synthesis of Reversible Logic Using Evolutionary Algorithms. EvoApplications (2) 2011: 151-161
- [c261]Marc Michael, Daniel Große, Rolf Drechsler: Analyzing dependability measures at the Electronic System Level. FDL 2011: 1-8
- [c260]Sebastian Offermann, Robert Wille, Rolf Drechsler: Efficient realization of control logic in reversible circuits. FDL 2011: 1-7
- [c259]Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler: Simulation-based equivalence checking between SystemC models at different levels of abstraction. ACM Great Lakes Symposium on VLSI 2011: 223-228
- [c258]Rolf Drechsler, Robert Wille: From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits. ISMVL 2011: 78-85
- [c257]Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler: Designing a RISC CPU in Reversible Logic. ISMVL 2011: 170-175
- [c256]Robert Wille, Hongyan Zhang, Rolf Drechsler: ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization. ISVLSI 2011: 120-125
- [c255]Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler: Towards Automatic Property Generation for the Formal Verification of Bus Bridges. MBMV 2011: 183-192
- [c254]Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler: Designing a RISC CPU in Reversible Logic. MBMV 2011: 249-258
- [c253]Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler: Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction. MBMV 2011: 269-278
- [c252]Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler: RevKit: An Open Source Toolkit for the Design of Reversible Circuits. RC 2011: 64-76
- [c251]Mathias Soeken, Robert Wille, Rolf Drechsler: Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models. TAP 2011: 152-170
- [e7]Cecilia Di Chio, Anthony Brabazon, Gianni A. Di Caro, Rolf Drechsler, Muddassar Farooq, Jörn Grahl, Gary Greenfield, Christian Prins, Juan Romero, Giovanni Squillero, Ernesto Tarantino, Andrea Tettamanzi, Neil Urquhart, A. Sima Etaner-Uyar (Eds.): Applications of Evolutionary Computation - EvoApplications 2011: EvoCOMNET, EvoFIN, EvoHOT, EvoMUSART, EvoSTIM, and EvoTRANSLOG, Torino, Italy, April 27-29, 2011, Proceedings, Part II. Lecture Notes in Computer Science 6625, Springer 2011, ISBN 978-3-642-20519-4
- 2010
- [b9]Robert Wille, Rolf Drechsler: Towards a Design Flow for Reversible Logic. Springer 2010, ISBN 978-90-481-9578-7, pp. I-XIII, 1-184
- [b8]Frank Rogin, Rolf Drechsler: Debugging at the Electronic System Level. Springer 2010, ISBN 978-90-481-9254-0, pp. I-XIX, 1-199
- [b7]
- [j61]Robert Wille, Rolf Drechsler: Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic. Electr. Notes Theor. Comput. Sci. 253(6): 57-70 (2010)
- [j60]Ulrich Kühne, Daniel Große, Rolf Drechsler: Towards Fully Automatic Synthesis of Embedded Software. Embedded Systems Letters 2(3): 53-57 (2010)
- [j59]Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler: MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. J. Electronic Testing 26(3): 307-322 (2010)
- [j58]Robert Wille, Rolf Drechsler: BDD-Based Synthesis of Reversible Logic. Int. J. of Applied Metaheuristic Computing 1(4): 25-41 (2010)
- [j57]Robert Wille, Rolf Drechsler: Synthese reversibler Logik (Synthesizing Reversible Logic). it - Information Technology 52(1): 30-38 (2010)
- [j56]Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler: Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits). it - Information Technology 52(4): 216-223 (2010)
- [j55]Daniel Tille, Stephan Eggersglüß, Rolf Drechsler: Incremental Solving Techniques for SAT-based ATPG. IEEE Trans. on CAD of Integrated Circuits and Systems 29(7): 1125-1130 (2010)
- [c250]Robert Wille, Mathias Soeken, Rolf Drechsler: Reducing the number of lines in reversible circuits. DAC 2010: 647-652
- [c249]Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler: Verifying UML/OCL models using Boolean satisfiability. DATE 2010: 1341-1344
- [c248]Rolf Drechsler, Görschwin Fey: Formal verification meets robustness checking - Techniques and challenges. DDECS 2010: 4
- [c247]Stefan Frehse, Görschwin Fey, Rolf Drechsler: A better-than-worst-case robustness measure. DDECS 2010: 78-83
- [c246]Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Synthesizing multiplier in reversible logic. DDECS 2010: 335-340
- [c245]Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Window optimization of reversible and quantum circuits. DDECS 2010: 341-345
- [c244]Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler: RobuCheck: A Robustness Checker for Digital Circuits. DSD 2010: 226-231
- [c243]Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler: Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. European Test Symposium 2010: 176-181
- [c242]Robert Wille, Sebastian Offermann, Rolf Drechsler: SyReC: A Programming Language for Synthesis of Reversible Circuits. FDL 2010: 184-189
- [c241]André Sülflow, Rolf Drechsler: Automatic Fault Localization for Programmable Logic Controllers. FORMS/FORMAT 2010: 247-256
- [c240]Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler: Enhancing debugging of multiple missing control errors in reversible logic. ACM Great Lakes Symposium on VLSI 2010: 465-470
- [c239]Hoang M. Le, Daniel Große, Rolf Drechsler: Towards analyzing functional coverage in SystemC TLM property checking. HLDVT 2010: 67-74
- [c238]Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler: Polynomial datapath optimization using constraint solving and formal modelling. ICCAD 2010: 756-761
- [c237]André Sülflow, Görschwin Fey, Rolf Drechsler: Using QBF to increase accuracy of SAT-based debugging. ISCAS 2010: 641-644
- [c236]Stephan Eggersglüß, Daniel Tille, Rolf Drechsler: Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation. ISCAS 2010: 649-652
- [c235]Alexander Finder, Rolf Drechsler: An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions. ISMVL 2010: 150-155
- [c234]Stefan Frehse, Robert Wille, Rolf Drechsler: Efficient Simulation-Based Debugging of Reversible Logic. ISMVL 2010: 156-161
- [c233]D. Michael Miller, Robert Wille, Rolf Drechsler: Reducing Reversible Circuit Cost by Adding Lines. ISMVL 2010: 217-222
- [c232]Robert Wille, Sebastian Offermann, Rolf Drechsler: SyReC: A Programming Language for Synthesis of Reversible Circuits. MBMV 2010: 21-30
- [c231]Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler: Verifying UML/OCL Models Using Boolean Satisfiability. MBMV 2010: 57-66
- [c230]Daniel Große, Hoang M. Le, Rolf Drechsler: Proving transaction and system-level properties of untimed SystemC TLM designs. MEMOCODE 2010: 113-122
- [c229]Görschwin Fey, André Sülflow, Rolf Drechsler: Towards Unifying Localization and Explanation for Automated Debugging. MTV 2010: 3-8
- [c228]Hoang M. Le, Daniel Große, Rolf Drechsler: Automatic Fault Localization for SystemC TLM Designs. MTV 2010: 35-40
2000 – 2009
- 2009
- [b6]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille: Test Pattern Generation using Boolean Proof Engines. Springer 2009, ISBN 978-90-481-2359-9, pp. I-XII, 1-192
- [j54]Rüdiger Ebendt, Rolf Drechsler: Weighted A* search - unifying view and application. Artif. Intell. 173(14): 1310-1342 (2009)
- [j53]Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke: Advanced verification by automatic property generation. IET Computers & Digital Techniques 3(4): 338-353 (2009)
- [j52]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille: Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). it - Information Technology 51(2): 102-111 (2009)
- [j51]Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Synthesis of Elementary Quantum Gate Circuits. Multiple-Valued Logic and Soft Computing 15(4): 283-300 (2009)
- [j50]Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 703-715 (2009)
- [c227]Stephan Eggersglüß, Daniel Tille, Rolf Drechsler: Speeding up SAT-Based ATPG Using Dynamic Clause Activation. Asian Test Symposium 2009: 177-182
- [c226]Görschwin Fey, André Sülflow, Rolf Drechsler: Computing bounds for fault tolerance using formal techniques. DAC 2009: 190-195
- [c225]Robert Wille, Rolf Drechsler: BDD-based synthesis of reversible logic for large functions. DAC 2009: 270-275
- [c224]Christian Genz, Rolf Drechsler: Overcoming limitations of the SystemC data introspection. DATE 2009: 590-593
- [c223]Ulrich Kühne, Daniel Große, Rolf Drechsler: Property analysis and design understanding. DATE 2009: 1246-1249
- [c222]Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler: Debugging of Toffoli networks. DATE 2009: 1284-1289
- [c221]André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler: Increasing the accuracy of SAT-based debugging. DATE 2009: 1326-1331
- [c220]
- [c219]Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler: Robustness Check for Multiple Faults Using Formal Techniques. DSD 2009: 85-90
- [c218]Stephan Eggersglüß, Rolf Drechsler: Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques. European Test Symposium 2009: 81-86
- [c217]Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler: SMT-based stimuli generation in the SystemC Verification library. FDL 2009: 1-6
- [c216]Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler: Contradictory antecedent debugging in bounded model checking. ACM Great Lakes Symposium on VLSI 2009: 173-176
- [c215]Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler: Timing Arc based logic analysis for false noise reduction. ICCAD 2009: 225-230
- [c214]
- [c213]André Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler: Evaluation of Cardinality Constraints on SMT-Based Debugging. ISMVL 2009: 298-303
- [c212]Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler: Equivalence Checking of Reversible Circuits. ISMVL 2009: 324-330
- [c211]André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler: Increasing the Accuracy of SAT-based Debugging. MBMV 2009: 47-56
- [c210]Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler: Equivalence Checking of Reversible Circuits. MBMV 2009: 67-76
- [c209]Daniel Große, Hoang M. Le, Rolf Drechsler: Induction-Based Formal Verification of SystemC TLM Designs. MTV 2009: 101-106
- [c208]André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler: WoLFram- A Word Level Framework for Formal Verification. IEEE International Workshop on Rapid System Prototyping 2009: 11-17
- [c207]Frank Rogin, Rolf Drechsler, Steffen Rülke: Automatic debugging of System-on-a-Chip designs. SoCC 2009: 333-336
- [c206]Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler: Reversible Logic Synthesis with Output Permutation. VLSI Design 2009: 189-194
- [p1]Rolf Drechsler, Tommi A. Junttila, Ilkka Niemelä: Non-Clausal SAT and ATPG. Handbook of Satisfiability 2009: 655-693
- 2008
- [b5]Görschwin Fey, Rolf Drechsler: Robustness and usability in modern design flows. Springer 2008, ISBN 978-1-4020-6535-4, pp. I-XIII, 1-166
- [j49]Sean Safarpour, Andreas G. Veneris, Rolf Drechsler: Improved SAT-based Reachability Analysis with Observability Don't Cares. JSAT 5(1-4): 1-25 (2008)
- [j48]Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler: On the construction of small fully testable circuits with low depth. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 263-269 (2008)
- [j47]Sebastian Kinder, Rolf Drechsler: Modeling and proving functional completeness in formal verification of counting heads. STTT 10(6): 521-534 (2008)
- [j46]Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler: Automatic Fault Localization for Property Checking. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1138-1149 (2008)
- [j45]Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa: Logic Minimization and Testability of 2-SPP Networks. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1190-1202 (2008)
- [j44]Daniel Große, Ulrich Kühne, Rolf Drechsler: Analyzing Functional Coverage in Bounded Model Checking. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1305-1314 (2008)
- [j43]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille: On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1329-1333 (2008)
- [c205]Sujan Pandey, Rolf Drechsler: Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival. ASP-DAC 2008: 601-606
- [c204]Sujan Pandey, Rolf Drechsler: Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs. DATE 2008: 206-211
- [c203]Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke: Automatic Generation of Complex Properties for Hardware Designs. DATE 2008: 545-548
- [c202]Daniel Tille, Rolf Drechsler: Incremental SAT Instance Generation for SAT-based ATPG. DDECS 2008: 68-73
- [c201]Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler: Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. DSD 2008: 542-549
- [c200]Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler: Contradiction Analysis for Constraint-based Random Simulation. FDL 2008: 130-135
- [c199]André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler: Using unsatisfiable cores to debug multiple design errors. ACM Great Lakes Symposium on VLSI 2008: 77-82
- [c198]Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner: Process variations aware robust on-chip bus architecture synthesis for MPSoCs. ISCAS 2008: 2989-2992
- [c197]Doina Logofatu, Rolf Drechsler: Comparative Study by Solving the Test Compaction Problem. ISMVL 2008: 44-49
- [c196]Stephan Eggersglüß, Rolf Drechsler: On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults. ISMVL 2008: 94-99
- [c195]Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. ISMVL 2008: 214-219
- [c194]Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler: RevLib: An Online Resource for Reversible Functions and Reversible Circuits. ISMVL 2008: 220-225
- [c193]Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler: Adaptive Branch and Bound Using SAT to Estimate False Crosstalk. ISQED 2008: 508-513
- [c192]
- [c191]Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler: Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. ISVLSI 2008: 411-416
- [c190]André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler: Debugging Design Errors by Using Unsatisfiable Cores. MBMV 2008: 159-168
- [c189]Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler: Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking. MBMV 2008: 169-178
- [c188]Ulrich Kühne, Daniel Große, Rolf Drechsler: Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow. MTV 2008: 88-93
- [e6]Mario Giacobini, Anthony Brabazon, Stefano Cagnoni, Gianni Di Caro, Rolf Drechsler, Anikó Ekárt, Anna Esparcia-Alcázar, Muddassar Farooq, Andreas Fink, Jon McCormack, Michael O'Neill, Juan Romero, Franz Rothlauf, Giovanni Squillero, Sima Uyar, Shengxiang Yang (Eds.): Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. Proceedings. Lecture Notes in Computer Science 4974, Springer 2008, ISBN 978-3-540-78760-0
- 2007
- [j42]Sabine Glesner, Jens Knoop, Rolf Drechsler: Preface. Electr. Notes Theor. Comput. Sci. 190(4): 1-2 (2007)
- [j41]Beate Muranko, Rolf Drechsler: Technische Dokumentation von Soft- und Hardware in Eingebetteten Systemen (Technical Documentation of Soft- and Hardware in Embedded Systems). it - Information Technology 49(2): 110- (2007)
- [c187]Daniel Große, Ulrich Kühne, Rolf Drechsler: Estimating functional coverage in bounded model checking. DATE 2007: 1176-1181
- [c186]Daniel Tille, Görschwin Fey, Rolf Drechsler: Instance Generation for SAT-based ATPG. DDECS 2007: 153-156
- [c185]Sebastian Kinder, Rolf Drechsler: Proving Completeness of Properties in Formal Verification of Counting Heads for Railways. DSD 2007: 396-403
- [c184]Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler: On the Construction of Small Fully Testable Circuits with Low Depth. DSD 2007: 563-569
- [c183]Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke: An Integrated SystemC Debugging Environment. FDL 2007: 140-145
- [c182]Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler: Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques. FDL 2007: 146-151
- [c181]Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler: Exact sat-based toffoli network synthesis. ACM Great Lakes Symposium on VLSI 2007: 96-101
- [c180]Daniel Große, Rüdiger Ebendt, Rolf Drechsler: Improvements for constraint solving in the systemc verification library. ACM Great Lakes Symposium on VLSI 2007: 493-496
- [c179]Rolf Drechsler, Andreas Breiter: Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design?. ICSOFT (SE) 2007: 409-416
- [c178]Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard: Visualization of SystemC Designs. ISCAS 2007: 413-416
- [c177]Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler: SAT-based ATPG for Path Delay Faults in Sequential Circuits. ISCAS 2007: 3671-3674
- [c176]Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL 2007: 6
- [c175]André Sülflow, Rolf Drechsler: Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC. ISMVL 2007: 42
- [c174]Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler: Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. ISMVL 2007: 50
- [c173]Ulrich Kühne, Daniel Große, Rolf Drechsler: Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. ISVLSI 2007: 165-170
- [c172]Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler: Formal Verification on the Word Level using SAT-like Proof Techniques. MBMV 2007: 81-90
- [c171]André Sülflow, Görschwin Fey, Rolf Drechsler: Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse. MBMV 2007: 101-110
- [c170]Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. MEMOCODE 2007: 181-187
- [c169]Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler: SWORD: A SAT like prover using word level information. VLSI-SoC 2007: 88-93
- [c168]Sujan Pandey, Christian Genz, Rolf Drechsler: Co-synthesis of custom on-chip bus and memory for MPSoC architectures. VLSI-SoC 2007: 304-307
- [c167]Görschwin Fey, Tim Warode, Rolf Drechsler: Reusing Learned Information in SAT-based ATPG. VLSI Design 2007: 69-76
- [e5]Mario Giacobini, Anthony Brabazon, Stefano Cagnoni, Gianni Di Caro, Rolf Drechsler, Muddassar Farooq, Andreas Fink, Evelyne Lutton, Penousal Machado, Stefan Minner, Michael O'Neill, Juan Romero, Franz Rothlauf, Giovanni Squillero, Hideyuki Takagi, Sima Uyar, Shengxiang Yang (Eds.): Applications of Evolutinary Computing, EvoWorkshops 2007: EvoCoMnet, EvoFIN, EvoIASP,EvoINTERACTION, EvoMUSART, EvoSTOC and EvoTransLog, Valencia, Spain, April11-13, 2007, Proceedings. Lecture Notes in Computer Science 4448, Springer 2007, ISBN 978-3-540-71804-8
- 2006
- [j40]Görschwin Fey, Rolf Drechsler: Minimizing the number of paths in BDDs: Theory and algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 4-11 (2006)
- [j39]Rüdiger Ebendt, Rolf Drechsler: Effect of improved lower bounds in dynamic BDD reordering. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 902-909 (2006)
- [j38]Valentina Ciriani, Anna Bernasconi, Rolf Drechsler: Testability of SPP Three-Level Logic Networks in Static Fault Models. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2241-2248 (2006)
- [c166]Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler: On the relation between simulation-based and SAT-based diagnosis. DATE 2006: 1139-1144
- [c165]Görschwin Fey, Daniel Große, Rolf Drechsler: Avoiding false negatives in formal verification for protocol-driven blocks. DATE 2006: 1225-1226
- [c164]Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa: Efficient minimization of fully testable 2-SPP networks. DATE 2006: 1300-1305
- [c163]André Sülflow, Nicole Drechsler, Rolf Drechsler: Robust Multi-Objective Optimization in High Dimensional Spaces. EMO 2006: 715-726
- [c162]Doina Logofatu, Rolf Drechsler: Efficient Evolutionary Approaches for the Data Ordering Problem with Inversion. EvoWorkshops 2006: 320-331
- [c161]Daniel Große, Ulrich Kühne, Rolf Drechsler: HW/SW co-verification of embedded systems using bounded model checking. ACM Great Lakes Symposium on VLSI 2006: 43-48
- [c160]Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler: Automatic Fault Localization for Property Checking. Haifa Verification Conference 2006: 50-64
- [c159]Rüdiger Ebendt, Rolf Drechsler: On the sensitivity of BDDs with respect to path-related objective functions. ISCAS 2006
- [c158]Sean Safarpour, Andreas G. Veneris, Rolf Drechsler: Integrating observability don't cares in all-solution SAT solvers. ISCAS 2006
- [c157]Görschwin Fey, Junhao Shi, Rolf Drechsler: Efficiency of Multi-Valued Encoding in SAT-based ATPG. ISMVL 2006: 25
- [c156]
- [c155]Rüdiger Ebendt, Rolf Drechsler: A Framework for Quasi-exact Optimization Using Relaxed Best-First Search. KI 2006: 331-345
- [c154]Görschwin Fey, Rolf Drechsler: SAT-based Calculation of Source Code Coverage for BMC. MBMV 2006: 163-170
- [c153]Beate Muranko, Rolf Drechsler: Technische Dokumentation von Soft- und Hardware-Systemen: Die vergessene Welt. MBMV 2006: 227-231
- [c152]
- [c151]Beate Muranko, Rolf Drechsler: Technical Documentation of Software and Hardware in Embedded Systems. VLSI-SoC 2006: 261-266
- [c150]Rolf Drechsler, Görschwin Fey, Sebastian Kinder: An Integrated Approach for Combining BDD and SAT Provers. VLSI Design 2006: 237-242
- [e4]Franz Rothlauf, Jürgen Branke, Stefano Cagnoni, Ernesto Costa, Carlos Cotta, Rolf Drechsler, Evelyne Lutton, Penousal Machado, Jason H. Moore, Juan Romero, George D. Smith, Giovanni Squillero, Hideyuki Takagi (Eds.): Applications of Evolutionary Computing, EvoWorkshops 2006: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoINTERACTION, EvoMUSART, and EvoSTOC, Budapest, Hungary, April 10-12, 2006, Proceedings. Lecture Notes in Computer Science 3907, Springer 2006, ISBN 3-540-33237-5
- 2005
- [b4]Rüdiger Ebendt, Görschwin Fey, Rolf Drechsler: Advanced BDD optimization. Springer 2005, ISBN 978-0-387-25453-1, pp. I-X, 1-222
- [j37]Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler: Combining ordered best-first search with branch and bound for exact BDD minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1515-1529 (2005)
- [c149]Junhao Shi, Görschwin Fey, Rolf Drechsler: Bridging fault testability of BDD circuits. ASP-DAC 2005: 188-191
- [c148]
- [c147]Daniel Große, Rolf Drechsler: Acceleration of SAT-Based Iterative Property Checking. CHARME 2005: 349-353
- [c146]Daniel Große, Ulrich Kühne, Rolf Drechsler: Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors. GI Jahrestagung (1) 2005: 308-312
- [c145]Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler: Utilizing don't care states in SAT-based bounded sequential problems. ACM Great Lakes Symposium on VLSI 2005: 264-269
- [c144]Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler: Post-verification debugging of hierarchical designs. ICCAD 2005: 871-876
- [c143]Daniel Große, Rolf Drechsler: CheckSyC: an efficient property checker for RTL SystemC designs. ISCAS (4) 2005: 4167-4170
- [c142]Sebastian Kinder, Görschwin Fey, Rolf Drechsler: Controlling the Memory During Manipulation of Word-Level Decision Diagrams. ISMVL 2005: 250-255
- [c141]Rüdiger Ebendt, Rolf Drechsler: Quasi-Exact BDD Minimization Using Relaxed Best-First Search. ISVLSI 2005: 59-64
- [c140]Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. ISVLSI 2005: 212-217
- [c139]Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler: Post-Verification Debugging of Hierarchical Designs. MTV 2005: 42-47
- [c138]Daniel Große, Ulrich Kühne, Rolf Drechsler: HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. MTV 2005: 133-137
- [c137]Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große: SyCE: An Integrated Environment for System Design in SystemC. IEEE International Workshop on Rapid System Prototyping 2005: 258-260
- [c136]Rüdiger Ebendt, Rolf Drechsler: Exact BDD Minimization for Path-Related Objective Functions. VLSI-SoC 2005: 299-315
- [e3]Franz Rothlauf, Jürgen Branke, Stefano Cagnoni, David W. Corne, Rolf Drechsler, Yaochu Jin, Penousal Machado, Elena Marchiori, Juan Romero, George D. Smith, Giovanni Squillero (Eds.): Applications of Evolutionary Computing, EvoWorkshops 2005: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoMUSART, and EvoSTOC, Lausanne, Switzerland, March 30 - April 1, 2005, Proceedings. Lecture Notes in Computer Science 3449, Springer 2005, ISBN 3-540-25396-3
- 2004
- [j36]Rolf Drechsler, Junhao Shi, Görschwin Fey: Synthesis of fully testable circuits from BDDs. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 440-443 (2004)
- [c135]Görschwin Fey, Rolf Drechsler: Improving simulation-based verification by means of formal methods. ASP-DAC 2004: 640-643
- [c134]Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler: Minimization of the expected path length in BDDs based on local changes. ASP-DAC 2004: 865-870
- [c133]Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler: Combining ordered best-first search with branch and bound for exact BDD minimization. ASP-DAC 2004: 875-878
- [c132]Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee: Managing Don't Cares in Boolean Satisfiability. DATE 2004: 260-265
- [c131]Görschwin Fey, Junhao Shi, Rolf Drechsler: BDD Circuit Optimization for Path Delay Fault Testability. DSD 2004: 168-172
- [c130]Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler: Disjoint Sum of Product Minimization by Evolutionary Algorithms. EvoWorkshops 2004: 198-207
- [c129]Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir: Debugging sequential circuits using Boolean satisfiability. ICCAD 2004: 204-209
- [c128]Thomas Eschbach, Rolf Drechsler, Bernd Becker: Placement and routing optimization for circuits derived from BDDs. ISCAS (5) 2004: 229-232
- [c127]Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler: Reduction of Sizes of Multi-Valued Decision Diagrams by Copy Propertie. ISMVL 2004: 223-228
- [c126]Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski: Algorithms for Taylor Expansion Diagrams. ISMVL 2004: 235-240
- [c125]
- [c124]
- [c123]Rolf Drechsler, Wolfgang Günther, Burkhard Stubert: Efficient (Non-)Reachability Analysis of Counterexamples. MBMV 2004: 250-259
- [c122]
- [c121]Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Freescale Semiconductor, Rolf Drechsler, Alexander Smith: Debugging Sequential Circuits Using Boolean Satisfiability. MTV 2004: 44-49
- [c120]Rolf Drechsler: Towards Formal Verification on the System Level. IEEE International Workshop on Rapid System Prototyping 2004: 2-5
- [e2]Günther R. Raidl, Stefano Cagnoni, Jürgen Branke, David Corne, Rolf Drechsler, Yaochu Jin, Colin G. Johnson, Penousal Machado, Elena Marchiori, Franz Rothlauf, George D. Smith, Giovanni Squillero (Eds.): Applications of Evolutionary Computing, EvoWorkshops 2004: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoMUSART, and EvoSTOC, Coimbra, Portugal, April 5-7, 2004, Proceedings. Lecture Notes in Computer Science 3005, Springer 2004, ISBN 3-540-21378-3
- 2003
- [j35]Martin Keim, Rolf Drechsler, Bernd Becker, Michael Martin, Paul Molitor: Polynomial Formal Verification of Multipliers. Formal Methods in System Design 22(1): 39-58 (2003)
- [j34]Daniel Große, Rolf Drechsler: Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC. it - Information Technology 45(4): 219-226 (2003)
- [j33]Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst: Recursive bi-partitioning of netlists for large number of partitions. Journal of Systems Architecture 49(12-15): 521-528 (2003)
- [j32]Frank Schmiedle, Rolf Drechsler, Bernd Becker: Exact Routing with Search Space Reduction. IEEE Trans. Computers 52(6): 815-825 (2003)
- [j31]Wolfgang Günther, Rolf Drechsler: Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams. IEEE Trans. Computers 52(9): 1196-1209 (2003)
- [j30]Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler: An improved branch and bound algorithm for exact BDD minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 22(12): 1657-1663 (2003)
- [c119]Rolf Drechsler, Nicole Drechsler: Minimization of Transitions by Complementation and Resequencing using Evolutionary Algorithms. Applied Informatics 2003: 109-114
- [c118]Junhao Shi, Görschwin Fey, Rolf Drechsler: BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. Asian Test Symposium 2003: 290-293
- [c117]Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler: Combination of Lower Bounds in Exact BDD Minimization. DATE 2003: 10758-10763
- [c116]Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler: Fast Heuristics for the Edge Coloring of Large Graphs. DSD 2003: 230-239
- [c115]Rolf Drechsler, Nicole Drechsler: GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages. EvoWorkshops 2003: 378-387
- [c114]Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst: Efficient Automatic Visualization of SystemC Designs. FDL 2003: 646-658
- [c113]Rolf Drechsler, Junhao Shi, Görschwin Fey: MuTaTe: an efficient design for testability technique for multiplexor based circuits. ACM Great Lakes Symposium on VLSI 2003: 80-83
- [c112]
- [c111]Daniel Große, Rolf Drechsler: Formal verification of LTL formulas for SystemC designs. ISCAS (5) 2003: 245-248
- [c110]Rolf Drechsler: Synthesizing checkers for on-line verification of System-on-Chip designs. ISCAS (4) 2003: 748-751
- [c109]Denis V. Popel, Rolf Drechsler: Efficient Minimization of Multiple-valued Decision Diagrams for Incompletely Specified Functions. ISMVL 2003: 241-246
- [c108]Daniel Große, Görschwin Fey, Rolf Drechsler: Modeling Multi-Valued Circuits in SystemC. ISMVL 2003: 281-286
- [c107]Görschwin Fey, Sebastian Kinder, Rolf Drechsler: Using Games for Benchmarking and Representing the Complete Solution Space using Symbolic Techniques. ISMVL 2003: 361-366
- [c106]D. Michael Miller, Rolf Drechsler: Augmented Sifting of Multiple-Valued Decision Diagrams. ISMVL 2003: 375-382
- [c105]Daniel Große, Rolf Drechsler: Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen. MBMV 2003: 229-238
- [c104]Görschwin Fey, Rolf Drechsler: Finding Good Counter-Examples to Aid Design Verification. MEMOCODE 2003: 51-
- [c103]Nicole Drechsler, Rolf Drechsler: Exploration of Sequential Depth by Evolutionary Algorithms. VLSI-SOC 2003: 81-85
- [c102]Valentina Ciriani, Anna Bernasconi, Rolf Drechsler: Testability of SPP Three-Level Logic Networks. VLSI-SOC 2003: 331-336
- [e1]Rolf Drechsler (Ed.): Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Bremen, Germany, February 24-25, 2003. Shaker 2003
- 2002
- [j29]Frank Schmiedle, Nicole Drechsler, Daniel Große, Rolf Drechsler: Heuristic Learning Based on Genetic Programming. Genetic Programming and Evolvable Machines 3(4): 363-388 (2002)
- [j28]
- [j27]
- [j26]Rolf Drechsler, Wolfgang Günther, Stefan Höreth: Minimization of Word-Level Decision Diagrams. Integration 33(1-2): 39-70 (2002)
- [c101]Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst: Recursive Bi-Partitioning of Netlists for Large Number of Partitions. DSD 2002: 38-44
- [c100]Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler: Decision Diagram Optimization Using Copy Properties. DSD 2002: 236-243
- [c99]Rolf Drechsler, Daniel Große: Reachability Analysis for Formal Verification of SystemC. DSD 2002: 337-340
- [c98]Thomas Eschbach, Wolfgang Günther, Rolf Drechsler, Bernd Becker: Crossing Reduction by Windows Optimization. Graph Drawing 2002: 285-294
- [c97]Whitney J. Townsend, Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller: Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations. ACM Great Lakes Symposium on VLSI 2002: 178-183
- [c96]Mikael Kerttu, Per Lindgren, Mitchell A. Thornton, Rolf Drechsler: Switching activity estimation of finite state machines for low power synthesis. ISCAS (4) 2002: 65-68
- [c95]D. Michael Miller, Rolf Drechsler: On the Construction of Multiple-Valued Decision Diagrams. ISMVL 2002: 245-253
- [c94]Rolf Drechsler: Evaluation of Static Variable Ordering Heuristics for MDD Construction. ISMVL 2002: 254-260
- [c93]Sherief Reda, Rolf Drechsler, Alex Orailoglu: On the Relation between SAT and BDDs for Equivalence Checking. ISQED 2002: 394-399
- [c92]Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller: Multi-Output Timed Shannon Circuits. ISVLSI 2002: 47-52
- [c91]Mikael Kerttu, Per Lindgren, Rolf Drechsler, Mitchell A. Thornton: Low Power Optimization Techniques for BDD Mapped Finite State Machines. IWLS 2002: 143-148
- [c90]Klaus-Jürgen Englert, Bernd Becker, Rolf Drechsler: Symbolic Simulation of Algorithms Specified in HDL. MBMV 2002: 113-122
- [c89]Rolf Drechsler, Jochen Römmler: Implementation and Visualization of a BDD Package in JAVA. MBMV 2002: 219-228
- [c88]Raik Brinkmann, Rolf Drechsler: RTL-Datapath Verification using Integer Linear Programming. VLSI Design 2002: 741-746
- 2001
- [b3]Mitchell Aaron Thornton, Rolf Drechsler, D. Michael Miller: Spectral techniques in VLSI CAD. Kluwer 2001, ISBN 978-0-7923-7433-6, pp. I-XIII, 1-250
- [j25]Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker: Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits. J. Electronic Testing 17(1): 37-51 (2001)
- [j24]Rolf Drechsler, Wolfgang Günther: History-based dynamic BDD minimization. Integration 31(1): 51-63 (2001)
- [j23]Rolf Drechsler: Äquivalenzvergleich digitaler Schaltungen im industriellen Umfeld (Equivalence Checking of Digital Circuits in an Industrial Environment). it+ti - Informationstechnik und Technische Informatik 43(4): 200-205 (2001)
- [j22]Rolf Drechsler, Detlef Sieling: Binary decision diagrams in theory and practice. STTT 3(2): 112-136 (2001)
- [j21]Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler: Decision Diagram Method for Calculation of Pruned Walsh Transform. IEEE Trans. Computers 50(2): 147-157 (2001)
- [j20]Rolf Drechsler, Wolfgang Günther, Fabio Somenzi: Using lower bounds during dynamic BDD minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 51-57 (2001)
- [c87]Per Lindgren, Mikael Kerttu, Mitchell A. Thornton, Rolf Drechsler: Low power optimization technique for BDD mapped circuits. ASP-DAC 2001: 615-621
- [c86]Mitchell A. Thornton, Rolf Drechsler: Spectral decision diagrams using graph transformations. DATE 2001: 713-719
- [c85]Bernd Becker, Thomas Eschbach, Rolf Drechsler, Wolfgang Günther: Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement. DSD 2001: 54-61
- [c84]Migyoung Jung, Gueesang Lee, Sungju Park, Rolf Drechsler: Minimization of OPKFDDs Using Genetic Algorithms. DSD 2001: 72-78
- [c83]Rolf Drechsler, Wolfgang Günther, Lothar Linhard, Gerhard Angst: Level Assignment for Displaying Combinational Logic. DSD 2001: 148-151
- [c82]Nicole Drechsler, Rolf Drechsler, Bernd Becker: Multi-objective Optimisation Based on Relation Favour. EMO 2001: 154-166
- [c81]Nicole Drechsler, Frank Schmiedle, Daniel Große, Rolf Drechsler: Heuristic Learning Based on Genetic Programming. EuroGP 2001: 1-10
- [c80]Frank Schmiedle, Daniel Große, Rolf Drechsler, Bernd Becker: Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics. Fuzzy Days 2001: 479-491
- [c79]Peer Johannsen, Rolf Drechsler: Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths. VLSI-SOC 2001: 361-374
- [c78]Frank Schmiedle, Wolfgang Günther, Rolf Drechsler: Selection of Efficient Re-Ordering Heuristics for MDD Construction. ISMVL 2001: 299-304
- [c77]
- [c76]Wolfgang Günther, Rolf Drechsler: Implementation of Read- k-times BDDs on Top of Standard BDD Packages. VLSI Design 2001: 173-178
- [c75]Wolfgang Günther, Rolf Drechsler: Performance Driven Optimization for MUX based FPGAs. VLSI Design 2001: 311-316
- 2000
- [j19]Rolf Drechsler, Bernd Becker, Nicole Drechsler: OKFDD minimization by genetic algorithms with application to circuit design. Integration 28(2): 121-139 (2000)
- [j18]A. Zuzek, Rolf Drechsler, Mitchell A. Thornton: Boolean function representation and spectral characterization using AND/OR graphs. Integration 29(2): 101-116 (2000)
- [j17]Wolfgang Günther, Rolf Drechsler: On the computational power of linearly transformed BDDs. Inf. Process. Lett. 75(3): 119-125 (2000)
- [j16]Wolfgang Günther, Rolf Drechsler: ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs. Journal of Systems Architecture 46(14): 1321-1334 (2000)
- [j15]Rolf Drechsler, Nicole Drechsler, Wolfgang Günther: Fast exact minimization of BDD's. IEEE Trans. on CAD of Integrated Circuits and Systems 19(3): 384-389 (2000)
- [c74]Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker: Verification of Designs Containing Black Boxes. EUROMICRO 2000: 1100-1105
- [c73]Wolfgang Günther, Rolf Drechsler: ACTion: Combining Logic Synthesis and Technology Mapping for MUX Based FPGAs. EUROMICRO 2000: 1130-1137
- [c72]Rolf Drechsler, Wolfgang Günther, Bernd Becker: Testability of Circuits Derived from Lattice Diagrams. EUROMICRO 2000: 1188-1192
- [c71]Rolf Drechsler, Nicole Drechsler, Elke Mackensen, Tobias Schubert, Bernd Becker: Design Reuse by Modularity: A Scalable Dynamical (Re)Configurable Multiprocessor System. EUROMICRO 2000: 1425-
- [c70]
- [c69]Tobias Schubert, Elke Mackensen, Nicole Drechsler, Rolf Drechsler, Bernd Becker: Specialized Hardware for Implementation of Evolutionary Algorithms. GECCO 2000: 369
- [c68]Rolf Drechsler, Wolfgang Günther: Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints. GECCO 2000: 513-518
- [c67]Wolfgang Günther, Rolf Drechsler, Stefan Höreth: Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation. ICCD 2000: 383-388
- [c66]Per Lindgren, Rolf Drechsler, Bernd Becker: Minimization of Ordered Pseudo Kronecker Decision Diagrams. ICCD 2000: 504-
- [c65]Rolf Drechsler, Mitchell A. Thornton, David Wessels: MDD-Based Synthesis of Multi-Valued Logic Networks. ISMVL 2000: 41-46
- [c64]Rolf Drechsler, Mitchell A. Thornton: Computation of Spectral Information from Logic Netlists. ISMVL 2000: 53-58
- [c63]Dragan Jankovic, Wolfgang Günther, Rolf Drechsler: Lower Bound Sifting for MDDs. ISMVL 2000: 193-198
- [c62]Frank Schmiedle, Wolfgang Günther, Rolf Drechsler: Dynamic Re-Encoding During MDD Minimization. ISMVL 2000: 239-244
- [c61]Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther: A Method for Approximate Equivalence Checking. ISMVL 2000: 447-452
- [c60]Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker: Verification of Designs Containing Black Boxes. MBMV 2000: 19-26
1990 – 1999
- 1999
- [j14]Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker: Testability of 2-Level AND/EXOR Circuits. J. Electronic Testing 14(3): 219-225 (1999)
- [j13]Rolf Drechsler: Preudo-Kronecker Expressions for Symmetric Functions. IEEE Trans. Computers 48(9): 987-990 (1999)
- [j12]Christoph Scholl, Dirk Möller, Paul Molitor, Rolf Drechsler: BDD minimization using symmetries. IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 81-100 (1999)
- [j11]Rolf Drechsler: Evolutionary Algorithms for VLSI CAD [book Review]. IEEE Trans. Evolutionary Computation 3(3): 251-253 (1999)
- [c59]Yibin Ye, Kaushik Roy, Rolf Drechsler: Power Consumption in XOR-Based Circuits. ASP-DAC 1999: 299-302
- [c58]Rolf Drechsler, Nicole Drechsler: Exploiting Don't Caers During Data Sequencing using Genetic Algorithms. ASP-DAC 1999: 303-
- [c57]
- [c56]Rolf Drechsler, Wolfgang Günther: Using Lower Bounds During Dynamic BDD Minimization. DAC 1999: 29-32
- [c55]
- [c54]Mitchell A. Thornton, J. P. Williams, Rolf Drechsler, Nicole Drechsler: Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities. DATE 1999: 758-759
- [c53]Rolf Drechsler, Wolfgang Günther: Generation of Optimal Universal Logic Modules. EUROMICRO 1999: 1080-1085
- [c52]Rolf Drechsler, Dragan Jankovic, Radomir S. Stankovic: Generic Implementation of DD Packages in MVL. EUROMICRO 1999: 1352-1359
- [c51]Rolf Drechsler: Checking Integrity During Dynamic Reordering in Decision Diagrams. EUROMICRO 1999: 1360-1367
- [c50]Nicole Drechsler, Wolfgang Günther, Rolf Drechsler: Efficient Graph Coloring by Evolutionary Algorithms. Fuzzy Days 1999: 30-39
- [c49]Nicole Drechsler, Rolf Drechsler, Bernd Becker: Multi-objected Optimization in Evolutionary Algorithms Using Satisfiability Classes. Fuzzy Days 1999: 108-117
- [c48]Wolfgang Günther, Rolf Drechsler: Efficient manipulation algorithms for linearly transformed BDDs. ICCAD 1999: 50-54
- [c47]Per Lindgren, Rolf Drechsler, Bernd Becker: Synthesis of Pseudo Kronecker Lattice Diagrams. ICCD 1999: 307-310
- [c46]Rolf Drechsler, Wolfgang Günther: History-Based Dynamic Minimization During BDD Construction. VLSI 1999: 334-345
- [c45]Wolfgang Günther, Rolf Drechsler: Minimization of BDDs using linear transformations based on evolutionary techniques. ISCAS (1) 1999: 387-390
- [c44]Frank Schmiedle, Rolf Drechsler, Bernd Becker: Exact channel routing using symbolic representation. ISCAS (6) 1999: 394-397
- [c43]Rolf Drechsler, Marc Herbstritt, Bernd Becker: Grouping heuristics for word-level decision diagrams. ISCAS (1) 1999: 411-414
- [c42]Franc Brglez, Rolf Drechsler: Design of experiments in CAD: context and new data sets for ISCAS'99. ISCAS (6) 1999: 424-427
- [c41]Wolfgang Günther, Rolf Drechsler: Creating hard problem instances in logic synthesis using exact minimization. ISCAS (6) 1999: 436-439
- [c40]Rolf Drechsler, Marc Herbstritt, Bernd Becker: Grouping Heuristics for Word-Level Decision Diagrams. MBMV 1999: 41-50
- 1998
- [b2]Rolf Drechsler, Bernd Becker: Graphenbasierte Funktionsdarstellung - Boolesche und Pseudo-Boolesche Funktionen. Leitfäden der Informatik, Teubner 1998, ISBN 978-3-519-02149-0, pp. 1-200
- [b1]Rolf Drechsler, Bernd Becker: Binary Decision Diagrams - Theory and Implementation. Springer 1998, ISBN 978-0-7923-8193-8, pp. I-X, 1-200
- [j10]Rolf Drechsler, Bernd Becker, Andrea Jahnke: On Variable Ordering and Decomposition Type Choice in OKFDDs. IEEE Trans. Computers 47(12): 1398-1403 (1998)
- [j9]Rolf Drechsler, Martin Sauerhoff, Detlef Sieling: The complexity of the inclusion operation on OFDD's. IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 457-459 (1998)
- [j8]Rolf Drechsler, Bernd Becker: Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions. IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 965-973 (1998)
- [c39]Gueesang Lee, Rolf Drechsler: ETDD-Based Synthesis of Term-Based FPGAs for Incompletely Specified Boolean Functions. ASP-DAC 1998: 75-80
- [c38]
- [c37]Rolf Drechsler, Nicole Drechsler, Wolfgang Günther: Fast Exact Minimization of BDDs. DAC 1998: 200-205
- [c36]Stefan Höreth, Rolf Drechsler: Dynamic Minimization of Word-Level Decision Diagrams. DATE 1998: 612-617
- [c35]Wolfgang Günther, Rolf Drechsler: Linear Transformations and Exact Minimization of BDDs. Great Lakes Symposium on VLSI 1998: 325-330
- [c34]D. Miller, Rolf Drechsler: Implementing a Multiple-Valued Decision Diagram Package. ISMVL 1998: 52-57
- [c33]Per Lindgren, Rolf Drechsler, Bernd Becker: Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions. ISMVL 1998: 95-
- [c32]Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker: Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm. ISMVL 1998: 215-
- [c31]
- 1997
- [j7]