José G. Delgado-Frias

Zhe Zhang, Michael A. Turi, José G. Delgado-Frias: SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells. ACM Great Lakes Symposium on VLSI 2012: 267-270

Jason Van Dyken, José G. Delgado-Frias: FPGA schemes for minimizing the power-throughput trade-off in executing the Advanced Encryption Standard algorithm. Journal of Systems Architecture - Embedded Systems Design 56(2-3): 116-123 (2010)

José G. Delgado-Frias, Zhe Zhang, Michael A. Turi: Low power SRAM cell design for FinFET and CNTFET technologies. Green Computing Conference 2010: 547-553

Ruirui Guo, José G. Delgado-Frias: IP Routing table compaction and sampling schemes to enhance TCAM cache performance. Journal of Systems Architecture - Embedded Systems Design 55(1): 61-69 (2009)

Michael A. Turi, José G. Delgado-Frias: Decreasing energy consumption in address decoders by means of selective precharge schemes. Microelectronics Journal 40(11): 1590-1600 (2009)

Kylan Robinson, José G. Delgado-Frias: Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures. ERSA 2009: 275-278

Michael A. Turi, José G. Delgado-Frias: High-Performance Low-Power Selective Precharge Schemes for Address Decoders. IEEE Trans. on Circuits and Systems 55-II(9): 917-921 (2008)

Mitchell J. Myjak, José G. Delgado-Frias: A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance. IEEE Trans. VLSI Syst. 16(1): 14-23 (2008)

Jason Van Dyken, José G. Delgado-Frias, Sirisha Medidi: FPGA Schemes with Optimized Routing for the Advanced Encryption Standard. ERSA 2008: 311-312

Michael A. Turi, José G. Delgado-Frias: High-performance low-power AND and Sense-Amp address decoders with selective precharging. ISCAS 2008: 1464-1467

Laurence Tianruo Yang, José G. Delgado-Frias, Yiming Li, Mohammed Y. Niamat, Dimitrios Soudris, Srinivasa Vemuru: Preface. Integration 40(2): 61 (2007)

Rongsen He, José G. Delgado-Frias: Fault Tolerant Interleaved Switching Fabrics For Scalable High-Performance Routers. IEEE Trans. Parallel Distrib. Syst. 18(12): 1727-1739 (2007)

H. Lin, José G. Delgado-Frias, Sirisha Medidi: Using a cache scheme to detect selfish nodes in mobile ad hoc networks. Communications, Internet, and Information Technology 2007: 61-66

H. Lui, José G. Delgado-Frias, Sirisha Medidi: Using a two-timer scheme to detect selfish nodes in mobile ad-hoc networks. Communications, Internet, and Information Technology 2007: 181-186

R. Guo, José G. Delgado-Frias: A novel compaction scheme for routing tables in TCAM to enhance cache hit rate. Communications, Internet, and Information Technology 2007: 210-215

Li Zhao, José G. Delgado-Frias: MARS: Misbehavior Detection in Ad Hoc Networks. GLOBECOM 2007: 941-945

Rongsen He, José G. Delgado-Frias: Redundant Array of Independent Fabrics - An Architecture for Next Generation Network. GLOBECOM 2007: 2763-2768

Hongxun Liu, José G. Delgado-Frias, Sirisha Medidi: Using a Cache Scheme to Detect Misbehaving Nodes in Mobile Ad-Hoc Networks. ICON 2007: 7-12

Daniel R. Blum, José G. Delgado-Frias: Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories. ISCAS 2007: 2786-2789

Rongsen He, José G. Delgado-Frias: Interleaved Multistage Switching Fabrics for Scalable High Performance Routers. GLOBECOM 2006

Mitchell J. Myjak, José G. Delgado-Frias: Superpipelined reconfigurable hardware for DSP. ISCAS 2006

Suryanarayana Tatapudi, José G. Delgado-Frias: A mesochronous pipeline scheme for high performance low power digital systems. ISCAS 2006

Li Zhao, José G. Delgado-Frias: Performance Analysis of Multipath Data Transmission in Multihop Ad Hoc Networks. SECON 2006: 927-932

Li Zhao, José G. Delgado-Frias: Multipath Routing Based Secure Data Transmission in Ad Hoc Networks. WiMob 2006: 17-23

Li Zhao, José G. Delgado-Frias: On Throughput of Multipath Data Transmission over Multihop Ad Hoc Networks. Wireless and Optical Communications 2006

Daniel R. Blum, Mitchell J. Myjak, José G. Delgado-Frias: Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS. CDES 2005: 28-34

Jin Liu, José G. Delgado-Frias: DAMQ Self-Compacting Buffer Schemes for Systems with Network-On-Chip. CDES 2005: 97-103

Mitchell J. Myjak, José G. Delgado-Frias: A Symmetric Differential Clock Generator for Bit-Serial Hardware. CDES 2005: 159-164

Suryanarayana Tatapudi, José G. Delgado-Frias: A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme. CDES 2005: 191-197

Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias: A distributed FIFO scheme for on chip communication. ISCAS (2) 2005: 1851-1854

Suryanarayana Tatapudi, José G. Delgado-Frias: A High Performance Hybrid Wave-Pipelined Multiplier. ISVLSI 2005: 282-283

Laurence Tianruo Yang, Hamid R. Arabnia, Yiming Li, Salam N. Salloum, José G. Delgado-Frias (Eds.): Proceedings of the 2005 International Conference on Computer Design, CDES 2005, Las Vegas, Nevada, USA, June 27-30, 2005. CSREA Press 2005, isbn 1-932415-54-8

Andy Widjaja, José G. Delgado-Frias: An H-Tree Based Configuration Scheme for Reconfigurable DSP Hardware. ESA/VLSI 2004: 530-535

Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias: A Distributed FIFO Scheme for System on Chip Inter-Component Communication. ESA/VLSI 2004: 536-540

Mitchell J. Myjak, Fredrick L. Anderson, José G. Delgado-Frias: H-Tree Interconnection Structure for Reconfigurable DSP Hardware. ERSA 2004: 170-176

Mitchell J. Myjak, José G. Delgado-Frias: Pipelined Multipliers for Reconfigurable Hardware. IPDPS 2004

Fred L. Anderson IV, José G. Delgado-Frias: A Reconfigurable Switch for a DSP Array. VLSI 2003: 3-6

Mitchell J. Myjak, José G. Delgado-Frias: A Two-Level Reconfigurable Architecture for Digital Signal Processing. VLSI 2003: 21-27

Daniel R. Blum, José G. Delgado-Frias: A Fault-Tolerant Memory-Based Cell for a Reconfigurable DSP Processor. VLSI 2003: 58-64

José G. Delgado-Frias, Girish B. Ratanpal: A VLSI wrapped wave front arbiter for crossbar switches. ACM Great Lakes Symposium on VLSI 2001: 85-88

Victor A. Skormin, José G. Delgado-Frias, Dennis L. McGee, Joseph Giordano, Leonard J. Popyack, Vladimir I. Gorodetski, Alexander O. Tarakanov: BASIS: A Biological Approach to System Information Security. MMM-ACNS 2001: 127-142

Stamatis Vassiliadis, Ming Zhang, José G. Delgado-Frias: Elementary function generators for neural-network emulators. IEEE Trans. Neural Netw. Learning Syst. 11(6): 1438-1449 (2000)

José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan: A wave-pipelined router architecture using ternary associative memory. ACM Great Lakes Symposium on VLSI 2000: 67-70

Valentine C. Aikens II, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis: A neuro-emulator with embedded capabilities for generalized learning. Journal of Systems Architecture 45(14): 1219-1243 (1999)

Chien-Ying Lu, José G. Delgado-Frias, Wei Lin: A Clustering and Genetic Scheme for Large Tsp Optimization Problems. Cybernetics and Systems 29(2): 137-157 (1998)

Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis: Executing tree routing algorithms on a high-performance pattern associative router. Journal of Systems Architecture 44(11): 849-866 (1998)

Douglas H. Summerville, José G. Delgado-Frias: Approaches for determining dynamic synchronization resource requirements. Computers and Their Applications 1998: 385-388

José G. Delgado-Frias, Jabulani Nyathi: A VLSI High-Performance Encoder with Priority Lookahead. Great Lakes Symposium on VLSI 1998: 59-64

José G. Delgado-Frias, Richard Diaz: A VLSI Self-Compacting Buffer for DAMQ Communication Switches. Great Lakes Symposium on VLSI 1998: 128-133

Adger E. Harvin III, José G. Delgado-Frias: A Dictionary Machine Emulation on a VLSI Computing Tree System. Great Lakes Symposium on VLSI 1998: 134-139

George Triantafyllos, Stamatis Vassiliadis, José G. Delgado-Frias: Software Metrics and Microcode: A Case Study. Journal of Software Maintenance 8(3): 199-224 (1996)

Ming Zhang, Stamatis Vassiliadis, José G. Delgado-Frias: Sigmoid Generators for Neural Computing Using Piecewise Approximations. IEEE Trans. Computers 45(9): 1045-1049 (1996)

Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis: A Flexible Bit-Pattern Associative Router for Interconnection Networks. IEEE Trans. Parallel Distrib. Syst. 7(5): 477-485 (1996)

Daniel G. Rice, José G. Delgado-Frias, Douglas H. Summerville: A Pattern-Associative Router for Interconnection Network Adaptive Algorithms. Euro-Par, Vol. I 1996: 213-217

José G. Delgado-Frias, Jabulani Nyathi, Chester L. Miller, Douglas H. Summerville: A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh. Great Lakes Symposium on VLSI 1996: 246-251

Joonho Park, Stamatis Vassiliadis, José G. Delgado-Frias: Flexible oblivious router architecture. IBM Journal of Research and Development 39(3): 315-330 (1995)

Weili Chu, Stamatis Vassiliadis, José G. Delgado-Frias: The multi-associative branch target buffer: a cost effective BTB mechanism. Microprocessing and Microprogramming 41(3): 211-225 (1995)

Valentine C. Aikens II, Steven M. Barber, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis: A Neuro-Architecture with Embedded Learning. Parallel and Distributed Computing and Systems 1995: 103-106

Daniel G. Rice, José G. Delgado-Frias, Douglas H. Summerville: A Pattern-Associative Router for Adaptive Algorithms in Hypercube Networks. Parallel and Distributed Computing and Systems 1995: 238-242

Adger E. Harvin III, José G. Delgado-Frias: A VLSI-Processing and Communicating Pipelined Tree for Parallel Computing. Parallel and Distributed Computing and Systems 1995: 455-458

Chuan-Jen Chang, Stamatis Vassiliadis, José G. Delgado-Frias: An investigation of binary CLA and ripple CMOS adder designs. Microprocessing and Microprogramming 40(1): 1-21 (1994)

Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis: A High Performance Pattern Associative Oblivious Router for Tree Topologies. IPPS 1994: 541-545

Joonho Park, Brian W. O'Krafka, Stamatis Vassiliadis, José G. Delgado-Frias: Design and evaluation of a DAMQ multiprocessor network with self-compacting buffers. SC 1994: 713-722

Robert H. Payne, José G. Delgado-Frias: MPU: A N-Tuple Matching Processor. ICCD 1991: 225-228

José G. Delgado-Frias, D. M. Green: BVE: a wafer-scale engine for differential equation computation. ICS 1988: 101-107