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André DeHon
2010 – today
- 2013
[c51]Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, André DeHon: GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction. FPGA 2013: 81-90- [c50]André DeHon: Location, location, location: the role of spatial locality in asymptotic energy minimization. FPGA 2013: 137-146
- [c49]
- 2012
- [j20]Nachiket Kapre, André DeHon: ${\rm SPICE}^2$: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA. IEEE Trans. on CAD of Integrated Circuits and Systems 31(1): 9-22 (2012)
- [c48]Nikil Mehta, Raphael Rubin, André DeHon: Limit study of energy & delay benefits of component-specific routing. FPGA 2012: 97-106
- [c47]Yutian Huan, André DeHon: FPGA optimized packet-switched NoC using split and merge primitives. FPT 2012: 47-52
- [c46]Udit Dhawan, Albert Kwon, Edin Kadric, Catalin Hritcu, Benjamin C. Pierce, Jonathan M. Smith, André DeHon, Gregory Malecha, Greg Morrisett, Thomas F. Knight Jr., Andrew Sutherland, Tom Hawkins, Amanda Zyxnfryx, David Wittenberg, Peter Trei, Sumit Ray, Greg Sullivan: Hardware Support for Safety Interlocks and Introspection. SASO Workshops 2012: 1-8
- 2011
- [j19]André DeHon, Benjamin Gojman: Crystals and Snowflakes: Building Computation from Nanowire Crossbars. IEEE Computer 44(2): 37-45 (2011)
- [j18]Nachiket Kapre, André DeHon: An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads. Int. J. Reconfig. Comp. 2011 (2011)
- [j17]Michael DeLorimier, Nachiket Kapre, Nikil Mehta, André DeHon: Spatial hardware implementation for sparse graph algorithms in GraphStep. TAAS 6(3): 17 (2011)
- [j16]Raphael Rubin, André DeHon: Choose-your-own-adventure routing: Lightweight load-time defect avoidance. TRETS 4(4): 33 (2011)
- [c45]Raphael Rubin, André DeHon: Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinder. FPGA 2011: 173-176
- [c44]Nachiket Kapre, André DeHon: VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration. FPT 2011: 1-9
- 2010
- [c43]André DeHon, Heather M. Quinn, Nicholas P. Carter: Vision for cross-layer optimization to address the dual challenges of energy and reliability. DATE 2010: 1017-1022
2000 – 2009
- 2009
- [j15]Benjamin Gojman, Harika Manem, Garrett S. Rose, André DeHon: Inversion schemes for sublithographic programmable logic arrays. IET Computers & Digital Techniques 3(6): 625-642 (2009)
- [j14]Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon: Pipelining Saturated Accumulation. IEEE Trans. Computers 58(2): 208-219 (2009)
- [j13]Helia Naeimi, André DeHon: Fault Secure Encoder and Decoder for NanoMemory Applications. IEEE Trans. VLSI Syst. 17(4): 473-486 (2009)
- [c42]
- [c41]Raphael Rubin, André DeHon: Choose-your-own-adventure routing: lightweight load-time defect avoidance. FPGA 2009: 23-32
- [c40]Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger: CMOS vs Nano: comrades or rivals? FPGA 2009: 121-122
- [c39]Nachiket Kapre, André DeHon: Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors. FPL 2009: 65-72
- [c38]Benjamin Gojman, André DeHon: VMATCH: Using logical variation to counteract physical variation in bottom-up, nanoscale systems. FPT 2009: 78-87
- 2008
- [j12]André DeHon, Mike Hutton: Guest Editorial: TRETS Special Edition on the 15th International Symposium on FPGAs. TRETS 1(1) (2008)
- 2007
- [j11]André DeHon, Craig S. Lent, Fabrizio Lombardi: Introduction to the Special Section on Nano Systems and Computing. IEEE Trans. Computers 56(2): 145-146 (2007)
- [j10]Kia Bazargan, André DeHon: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 201-202 (2007)
- [c37]Nachiket Kapre, André DeHon: Optimistic Parallelization of Floating-Point Accumulation. IEEE Symposium on Computer Arithmetic 2007: 205-216
- [c36]André DeHon, Jean-Louis Giavitto, Frédéric Gruau: 06361 Executive Report -- Computing Media Languages for Space-Oriented Computation. Computing Media and Languages for Space-Oriented Computation 2007
- [c35]André DeHon, Jean-Louis Giavitto, Frédéric Gruau: 06361 Abstracts Collection -- Computing Media Languages for Space-Oriented Computation. Computing Media and Languages for Space-Oriented Computation 2007
- [c34]Helia Naeimi, André DeHon: Fault Secure Encoder and Decoder for Memory Applications. DFT 2007: 409-417
- [e3]André DeHon, Jean-Louis Giavitto, Frédéric Gruau (Eds.): Computing Media and Languages for Space-Oriented Computation, 03.09. - 08.09.2006. Dagstuhl Seminar Proceedings 06361, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany 2007
- [e2]André DeHon, Mike Hutton (Eds.): Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007. ACM 2007, ISBN 978-1-59593-600-4
- 2006
- [j9]John E. Savage, Eric Rachlin, André DeHon, Charles M. Lieber, Yue Wu: Radial addressing of nanowires. JETC 2(2): 129-154 (2006)
- [j8]André DeHon, Randy Huang, John Wawrzynek: Stochastic spatial routing for reconfigurable networks. Microprocessors and Microsystems 30(6): 301-318 (2006)
- [j7]André DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek: Stream computations organized for reconfigurable execution. Microprocessors and Microsystems 30(6): 334-354 (2006)
- [c33]Michael G. Wrighton, André DeHon: SAT-based optimal hypergraph partitioning with replication. ASP-DAC 2006: 789-795
- [c32]Michael DeLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomas E. Uribe, Thomas F. Knight Jr., André DeHon: GraphStep: A System Architecture for Sparse-Graph Algorithms. FCCM 2006: 143-151
- [c31]Nachiket Kapre, Nikil Mehta, Michael DeLorimier, Raphael Rubin, Henry Barnor, Michael J. Wilson, Michael G. Wrighton, André DeHon: Packet Switched vs. Time Multiplexed FPGA Overlay Networks. FCCM 2006: 205-216
- [c30]Rajiv V. Joshi, Kaustav Banerjee, André DeHon: Tutorial 1: Emerging Technologies for VLSI Design. ISQED 2006: 4
- [e1]Steven J. E. Wilton, André DeHon (Eds.): Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006. ACM 2006, ISBN 1-59593-292-5
- 2005
- [j6]André DeHon, Helia Naeimi: Seven Strategies for Tolerating Highly Defective Fabrication. IEEE Design & Test of Computers 22(4): 306-315 (2005)
- [j5]
- [c29]Michael DeLorimier, André DeHon: Floating-point sparse matrix-vector multiply for FPGAs. FPGA 2005: 75-85
- [c28]André DeHon: Design of programmable interconnect for sublithographic programmable logic arrays. FPGA 2005: 127-137
- [c27]Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon: Pipelining Saturated Accumulation. FPT 2005: 19-26
- [c26]André DeHon, Konstantin Likharev: Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation. ICCAD 2005: 375-382
- 2004
- [j4]André DeHon, Raphael Rubin: Design of FPGA interconnect for multilevel metallization. IEEE Trans. VLSI Syst. 12(10): 1038-1050 (2004)
- [j3]André DeHon: Unifying mesh- and tree-based programmable interconnect. IEEE Trans. VLSI Syst. 12(10): 1051-1065 (2004)
- [c25]André DeHon, Joshua Adams, Michael DeLorimier, Nachiket Kapre, Yuki Matsuda, Helia Naeimi, Michael C. Vanier, Michael G. Wrighton: Design Patterns for Reconfigurable Computing. FCCM 2004: 13-23
- [c24]André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica: What is the right model for programming and using modern FPGAs? FPGA 2004: 119
- [c23]André DeHon, Michael J. Wilson: Nanowire-based sublithographic programmable logic arrays. FPGA 2004: 123-132
- [c22]Helia Naeimi, André DeHon: A greedy algorithm for tolerating defective crosspoints in nanoPLA design. FPT 2004: 49-56
- 2003
- [c21]Michael G. Wrighton, André DeHon: Hardware-assisted simulated annealing with application for fast FPGA placement. FPGA 2003: 33-42
- [c20]Randy Huang, John Wawrzynek, André DeHon: Stochastic, spatial routing for hypergraphs, trees, and meshes. FPGA 2003: 78-87
- [c19]Raphael Rubin, André DeHon: Design of FPGA interconnect for multilevel metalization. FPGA 2003: 154-163
- 2002
- [c18]
- [c17]Yury Markovsky, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, André DeHon: Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine. FPGA 2002: 196-205
- [c16]Michael Butts, André DeHon, Seth Copen Goldstein: Molecular electronics: devices, systems and tools for gigagate, gigabit chips. ICCAD 2002: 433-440
- [c15]
- 2001
- [c14]
- 2000
- [j2]
- [c13]Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHon: Stream Computations Organized for Reconfigurable Execution (SCORE). FPL 2000: 605-614
- [c12]
1990 – 1999
- 1999
- [c11]André DeHon, John Wawrzynek: Reconfigurable Computing: What, Why, and Implications for Design Automation. DAC 1999: 610-615
- [c10]André DeHon: Balancing Interconnect and Computation in a Reconfiguable Computing Array (or, why you don't really want 100% LUT utilization). FPGA 1999: 69-78
- [c9]William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, George Varghese, John Wawrzynek, André DeHon: HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array. FPGA 1999: 125-134
- 1998
- [c8]Michael Chu, Nicholas Weaver, Kolja Sulimma, André DeHon, John Wawrzynek: Object Oriented Circuit-Generators in Java. FCCM 1998: 158-166
- [c7]Timothy J. Callahan, Philip Chong, André DeHon, John Wawrzynek: Fast Module Mapping and Placement for Datapaths in FPGAs. FPGA 1998: 123-132
- 1997
- [j1]William H. Mangione-Smith, Brad Hutchins, David L. Andrews, André DeHon, Carl Ebeling, Reiner W. Hartenstein, Oskar Mencer, John Morris, Krishna V. Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg: Seeking Solutions in Configurable Computing. IEEE Computer 30(12): 38-43 (1997)
- [c6]
- 1996
- [c5]
- [c4]
- 1994
- [c3]Frederic T. Chong, Henry Minsky, André DeHon, Matthew Becker, Samuel Peretz, Eran Egozy, Thomas F. Knight Jr.: METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks. ISCA 1994: 266-277
- [c2]André DeHon: In-System Timing Extraction and Control Through Scan-Based, Test-Access Ports. ITC 1994: 350-359
- [c1]Ian Eslick, André DeHon, Thomas F. Knight Jr.: Guaranteeing Idempotence for Tightly-Coupled, Fault-Tolerant Networks. PCRCW 1994: 215-225
Coauthor Index
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last updated on 2013-10-02 11:23 CEST by the dblp team